Connection issue between C6678 DDR3 controller and the 8Gb DDR3 devices.

Jason,

The C6678 supports both single-rank and dual-rank SDRAM topologies.  Normally dual-rank topologies are implemented with single die devices so each rank must be leveled separately since the fly-by nets (address, command and control) must be length-matched to the clock.  However, when implementing a dual-rank topology using twin-die devices, the fly-by signals for both ranks are the same length.  Therefore, twin-die devices are fully supported.  The second clock output pair from the C6678 can be left unconnected.

I had not realized 8Gb twin-die devices were available yet.  Which manufacturer have you found with these available?

Tom

Hi Tom,

Thank you very much for your timely reply. We use DDR3 from Micron. 8Gb twin-die devices are available.

Hi Tom,

We connect 8 pieces of X8  8Gb  dual-rank DDR3 device on our board to implement a 64bit wide, dual-rank ,8GB DDR3 connection, 4 pieces on top side and  4 pieces on bottom side.

As you recommanded, we only use CK0 for CK connection of the DDR3 devices, leaving the second clock unconnected.

But  SI simulation show that the CK waveform is quite bad.

We had measured that CK0 and CK1 of C6678 has the same frequency and phase, so,

Can we use CK0 on the top side X8 devices (Byte0, byte2, byte4,byte6),

and use CK1 for the bottom side devices(Byte1,byte3,byte5,byte7)?

Is there any risk?

Thank you very much.

Jason,

No, I do not think that is the solution.  It will be impossible to meet the fly-by length matching rules.  How did you route the fly-by nets and meet the length matching rules with a top and bottom layout?  I would recommend that you keep the SDRAM memories all on one side for this topology.  Top and bottom is possible for a single-rank fly-by arrangement but it requires a lot of routing layers to obtain good signal integrity.  I recommend that you look at the JEDEC UDIMM spec.  It defines solutions for complex layouts.  Notably, it does not have any 2-sided single-rank layouts.  (Your twin-die SDRAM memories are effectively implemented in a single-rank layout.)  It also is very explicit about the stubs on the fly-by nets.  I will speculate that this is where you are having SI problems.  Fly-by layouts for DDR3 do not tolerate long stubs or branched stubs on a single-rank topology.

Tom

Hi Tom:

We want to put Byte0 device on top side and Byte1 on bottom side, so Byte0 and byte1 with the same length (Addr, Control signals..), Byte 2 and Byte3 devices with  the same length, etc..   CK0 and CK1 with the same topology .  Will this be right?

Thank you very much.

Jason,

Like I said previously, fly-by length matching will be very challenging in an interleaved top-bottom layout.  I am not sure it is even possible.  The standard UDIMM layouts do not do this.  Managing stub length will be very important.  They must be short and the length matched.

The other problem with top-bottom layout is data-group via stubs.  These are easily managed when the SOC and DRAMs are both on the top.  They cannot be easily managed with some DRAMs on the bottom.

Based on these issues, I recommend that the board needs to be laid out similar to one of the UDIMM standard layouts.  The topology that you created is beyond anything that we can support.  If you stay with the existing topology, you will need to improve the routing and validate this through simulation.

Tom

Hi Tom:

Our 8GB boards have come and we have done some DDR3 test on it.

We use 8 pieces of X8 8Gb device, 4 pieces on top side and 4 pieces on bottom side.

8Gb device has 2 Die in it and we use CK0 of C6678 for all  8 pieces of DDR3 device ,

leaving CK1 unconnected.

We test DDR3 for many of times.  Rank0 (CE0,4GB) works very robust, and have no error;

But Rank1(CE1, 4Gb) have many errors on byte 6 and byte7, which are the farest bytes  on the

fly-bye topology.   But byte6 and byte7 have the best signal integrity on our simulation.

Can you tell me why does this happen?

Thank you very much.

Hi Tom: We have done some more test on the 8GB DDR3 boards. Because there are errors on byte6 and byte7 for Rank1, and no error on Rank0, we do test as below:

1、Solder off the temination resister on CKE1, ODT1, and phenomenon is the same.

 2、Solder off the resisters on CE1, lots of errors occur, not only on byte 6 and byte7, all bytes on rank1 have errors, and what is more, data on CE0 also have some errors.

 3、We make C6678 to work on one rank mode and only rank0 of C6678 works, no error appears on Rank0.

 4、We Solder back the temination resister on CE1, there is no error on CE0. Can you tell me why this happen? I was really confused by the phenomenon? .

Could anybody here reply for me? The project has very urgent schedule and I am looking forward for the quick reply.

Thank you very much.

Jason,

I indicated many weeks back that this topology would be problematic and difficult for you to obtain success.  I cannot speculate the cause of difficulty.

What data rates have you tested?  Have you recalcualted the PHY_CALC init vlaues and the REG_CALC timing values for each rate tested?  Did you leave the termination and impedance settings unchanged from the REG_CALC sheet?

Tom

Hi Tom:

We have tested  1Gbps and 800Mbps DDR3 datarates and both have the same problem.

We have recalculated the PHY_CALC init values and REG_CALC timing values.

We have done many tests for different impendance settings ,including  unchanged  impedance settings from REG_CALC sheet.

The question is :

Rank 0 and Rank1 share the same data, address and control lines , why does rank0 work robustly but rank1 have so many errors?

Based on simulation, Byte6 and byte7 have the best siganal integrity , why do other bytes of Rank1 work robustly  but byte 6 and byte 7 have so many errors?

Hi Tom:

We have done more test about DDR3 of C6678 today.

We found that when we change the datarate of  DDR3 to 500MT/s, which means 250M CK clock output ,  the DDR3 controller can work robustly.

But I have one question:

I TI ducument SPRZ334F(errata) , DDR3 of C6678 can be configured to operate from 800MT/s to 1333MT/s.

What is the minimum transfer rate of C6678?

Does it  have any risk when we configureDDR3 of  C6678 to work below the transfer rate of 800MT/s?

Thank you very much.

Jason,

JEDEC defines DDR3 operation down to 666MTS (333MHz clock).

Tom

Hi Tom:

I learned from the datasheet of DDR3(Micron) that  DDR3 can work down to 300MT/s in DLL enabled mode and blow 125MT/s in DLL disabled mode.

Does C6678 have any limit  on the transfer speed of it`s DDR3 controller?

Jason,

I can only comment on the JEDEC required rates.  I expect it can operate at lower speeds as long as the memory supports it but I cannot guarantee it.  What speed are you running the Shannon during the memory tests?

Tom

.

Jason,

What is the latest status on this design?  We were intending to perform additional tests to resolve the dual-rank question but we wanted additional confirmation of the stability of the implementation first.  That was the point of the questions above.

Tom