Connection between MPU und ICSS

Robin Muller

Hello,

I have some questions about the PRUSS / ICSS.

1. How are the PRUS connected to the ARM core? In the Sitara EtherCAT whitepaper there is the following figure:

How are the arrows in the red circles realized?
In the Technical Reference Manual I read about a mailbox peripherial component on the chip. This makes sense for non-cyclical data, but how is the PDI realized?

2. In the AM335x datasheet there is a "functional block diagram" which shows "64K shared RAM". Is this used by ARM and PRUs?
If yes: How is it connected to the components and how fast is it?

I hope someone can help me getting started with the ICSS. I'm a bit confused because the Technoical Reference Manual doesn't contain any further information on the PRUSS and I didn't find a seperate document.

Regards,
Robin

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Robin,

There is a PRU-ICSS guide that can be found here: https://github.com/beagleboard/am335x_pru_package

0 Robin Muller over 12 years ago in reply to Biser Gatchev-XID

Prodigy 135 points

Thank your for the hint Biser. I'm a bit suprised that such important information is not provided on the official TI Homepage.

In the PRU Reference guide I found the following figure:

It shows that the ARM Core has an L4 interconnect to the PRU-ICSS which maybe will probably be used to program the firmware into the RAMs of the PRUs? Correct me if I'm wrong.
Coming back to the queston of my first post: How is the Data in a running application (for example an EtherCAT Slave Application) exchanged between ICSS and ARM Core? Is the L3 64k OCM-RAM of the AM335x, the 12k Shared RAM in the ICSS or different method used?

Regards,
Robin

0 PratheeshGangadhar over 12 years ago in reply to Robin Muller

TI__Mastermind 48571 points

Hi,

EtherCAT slave uses 12KB shared RAM in ICSS for ESC registers and process data memory implementation.

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Connection between MPU und ICSS