Mariana and others, for some reason, the previous questions I submitted cannot be found any more at E2E. Here is the update on what questions have been answered:
1. Okay. Just a comment: LVDS oscillators/drivers seem to consume a lot of current (100mA for the CDCM61001). This seems a bit contrary to the goal of minimum power consumption by the L138/L1808. A single-ended 75MHz or 100MHz input with the L138 generating the differential clocking would have been preferable.
2. Okay.
3. Does the VREF need to be at 0.9V when the SDRAM is in self-refresh? Can it be at 1.8V? The 1K-1K resistors will consume more power than the the SDRAM in self-refresh.
4. Not yet answered.
5. Okay: NAND Flash has been used with the L138 (I didn't want to design the board only to find that it doesn't work).
6. Okay.
7. Not yet answered.
8. Not yet answered.
9. Not yet answered.
10. Okay, but the note in the schematic says DNP.
11. Not yet answered.
12. Not yet answered.
13. Not yet answered.
14. Okay.
15. Is wakeup from RTC or DEEPSLEEP either/or under all condidtions? Or if (for example) DEEPSLEEP was entered using RTC, and only the RTC perform the wakeup?
Please add:
16. What is the behavior of nRESETOUT when in DEEPSLEEP?
17. Power-on sequence: Section 6.3.1 states:
There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than 2 volts.
If the 3.3V supply higher than the 1.8V supply by more than 2V, will this cause permanent damage to the L138 or just a malfunction? What if this only happens on power-down, but power-up is okay?
18. Which JTAG connector is recommended? There are a couple of options on the Logic PD schematic.
Questions I submitted at first time:
:1. SATA: is it necessary to pass the LVDS oscillator outputs through an RC network? I thought direct connections were possible.
2. If software is available to download the bootloader and OS through the serial port and Ethernet, is a JTAG connector necessary? Have other customers gotten by without JTAG?
3. For SDRAM, I'm using Mobile DDR, which does not have a DDR_VREF connection:
- Does the DDR_ZP resistor still need to be 0.5%? Note that a +/-100ppm/C temperature coefficient will result in an additional 0.7% error at -40C.
- Are 1K resistors required for the DDR_VREF divider or can they be a higher value? There is no VREF pin on Mobile DDR chips.
- Are series termination resistors required for DDR signals? Nothing is mentioned in any of the documentation, but the Logic PD schematic includes them.
4. Previously I asked about RS485 half-duplex, and the answer was that is it supported. For UART0 or UART1, can one the RTS or CTS pins be used to auto-switch the RS485 direction without software intervention?
5. Has NAND Flash programming through Serial and Ethernet been tested? I'm asking because Logic PD uses a serial flash device.
6. The oscillators are not using the OSCVSS and RTCVSS pins as recommended in Figure 6-6 of SPRS586A. Also, P. 69 states:
(2) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
7. Is a single filter for VDDA12_PLL0 and VDDA12_PLL1 acceptable? The filter caps are also on the wrong side of the ferrites in the Logic PD schematic, if Figure 6-8 of SPRS586A is correct.
8. Crystal bypass caps for 24 MHz: these are 33pF. The crystal has a load capacitance of 18pF. The load capacitance is normally Cbyp/2 + Cint, so this would indicate an L138 Cint of just 1.5pF. Is this accurate? I would have used around 27pF.
9. Crystal bypass caps for 32.768 KHz: these are 18pF. The crystal has a load capacitance of 12.5pF. This would indicated a Cint of 3.5pF. Is this accurate?
10. Are pullups required for SD? The schematic for the baseboard has the comment "These signals have internal pullups enabled by default", but has 4.7K pullups on the lines anyway.
11. Are 24.9R series and 15K pulldown resistors required for USB1? There is nothing in the documentation, but they are present in the schematic. Normally, 47pF caps are used on USB 1.1 lines, but these are not present in the schematic. Are they included internally in the L138?
12. I'm using USB PORT0 in host-only mode.
- Can the pulldown for USB0_ID be less than 10K?
- Connection of USB0_VBUS. Table-3 of SPRUFM9C:
5 volt input that signifies that VBUS is connected. The OTG section of the PHY can also pull-up/pull-down on this signal for HNP and SRP. For device or host only mode of operation, pull-up this pin to 5V with an external 1K ohm resistor. For host mode of operation, pull-up the USB power signal on the USB connector to 5V also. For mixed host/device mode of operation, tie this to the charge pump.
USB0_VBUS pulled up to 5V by 1K is clear enough for host only. I'm not sure what's meant by "pull-up the USB power signal on the USB connector to 5V also". The USB power signal on the connector should be connected directly to 5V, not pulled up.
13. SATA_REG and USB0_VDDA12: are the bypass caps 0.1uF (as documentation says for SATA_REG) or 0.22uF as in the schematic?
14. It doesn't appear that any of the USER LEDs can be controlled through software, only through the IO expander. Or is there a defined "Boot LED"?
15. The Logic PD schematic does not seem to use the DEEPSLEEP pin (it's used for UART2_CTS). The function of the DEEPSLEEP pin is not clear: is it an input or an output in Deep Sleep? How is the CPU woken up from the Deep Sleep state, other than an RTC interrupt? Can any GPIO be used?
