I2C time out on DM385 EVM

Kim Minsu

Prodigy 120 points

Other Parts Discussed in Thread: DM385

Dear all,

I have a two question on DM385 EVM.

Question 1) When I use i2c on dm385, does not working.
Please refer to below booting log.

Channel of I2C: 2
Device ID: 0x3C (OmniVision OV5640)

    [Booting Log]
    --------------------------------------------------------------------------------
     _____                    _____           _         _
    | _ |___ ___ ___ ___   | _ |___ ___ |_|___ ___| |_
    |     | _| .'| . | . | |   __| _| . | | | -_| _| _|
    |__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
                  |___|                    |___|

    Arago Project http://arago-project.org dm814x-evm ttyO0

    Arago 2011.09 dm814x-evm ttyO0

    dm814x-evm login: root (automatic login)
    root@dm814x-evm:~# mkdosfs 3.0.12 (29 Oct 2011)
    unable to get drive geometry, using default 255/63
    /dev/sbulla has 255 heads and 63 sectors per track,
    logical sector size is 512,
    using 0xf8 media descriptor, with 1024 sectors;
    file system has 2 12-bit FATs and 4 sectors per cluster.
    FAT size is 1 sector, and provides 247 clusters.
    There is 1 reserved sector.
    Root directory contains 512 slots and uses 32 sectors.
    Volume ID is 2891a25b, no volume label.
    g_file_storage gadget: No serial-number string provided!
    g_file_storage gadget: File-backed Storage Gadget, version: 1 September 2010
    g_file_storage gadget: Number of LUNs=1
    g_file_storage gadget-lun0: ro=0, nofua=0, file: /dev/sbulla
    Simple mixer control 'PGA',0
      Capabilities: cvolume cswitch penum
      Capture channels: Front Left - Front Right
      Limits: Capture 0 - 119
      Front Left: Capture 80 [67%] [40.00dB] [on]
      Front Right: Capture 80 [67%] [40.00dB] [on]
     [m3vpss ] I2C: timed out in wait_for_bb: I2C_IRQSTATUS=1000 !!!
     [m3vpss ] I2C2: DEV 0x3c: WR 0x3008 = 0x82 ... ERROR !!!
    queue id:0
    ApproDrvInit: 3
    Creat queue id:131076
    queue id:131076
    queue id:0
    ApproDrvInit: 7
    queue id:131076
     [m3vpss ] I2C: timed out in wait_for_bb: I2C_IRQSTATUS=1000 !!!
     [m3vpss ] I2C2: DEV 0x3c: WR 0x3008 = 0x42 ... ERROR !!!
     [m3vpss ] I2C: timed out in wait_for_bb: I2C_IRQSTATUS=1000 !!!
     [m3vpss ] I2C2: DEV 0x3c: WR 0x3103 = 0x03 ... ERROR !!!
     [m3vpss ] I2C: timed out in wait_for_bb: I2C_IRQSTATUS=1000 !!!
     [m3vpss ] I2C2: DEV 0x3c: WR 0x3017 = 0x00 ... ERROR !!!
     [m3vpss ] I2C: timed out in wait_for_bb: I2C_IRQSTATUS=1000 !!!
     [m3vpss ] I2C2: DEV 0x3c: WR 0x3018 = 0x00 ... ERROR !!!
    --------------------------------------------------------------------------------

What can I do for i2c on dm385?
Please let me know.

Question 2) As I know, The DM385 EVM has two I2C devices.

    Channel of I2C: 0
    Device ID: 0x18, 0x2D

    root@DM385_IPNC:/opt/ipnc# ./i2cdump 1 0x18
    No size specified (using byte-data access)
    Error: Could not set address to 0x18: Device or resource busy
    root@DM385_IPNC:/opt/ipnc# ./i2cdump 1 0x2d
    No size specified (using byte-data access)
    Error: Could not set address to 0x2d: Device or resource busy

    root@DM385_IPNC:/opt/ipnc# ./i2cdump 3 0x3C     <- OV5640
    No size specified (using byte-data access)
    Error: Could not set address to 0x3c: Device or resource busy
    root@DM385_IPNC:/opt/ipnc#

I don't know why device or resource busy.
Please let me know about this problem.

Thanks and Regards,
Minsu Kim

over 12 years ago

0 Kim Minsu over 12 years ago

Prodigy 120 points

Dear All,

I want to know about I2C register on DM385.
Please refer to below source code.
Is it correct?
If you know, please let me know.

Path: /GA_Release_3.5.0/ti_tools/iss_03_50_00_00/packages/ti/psp/devices/src/DM814x_i2c.h

    /*
     *====================
     * Defines
     *====================
     */
#define I2C0_BASE                    0x48028000
#define I2C1_BASE                    0x4802A000
#define I2C2_BASE                    0x4819C000
#define I2C3_BASE                    0x4819E000

    /* PRCM registers for I2C */
#define CM_ALWON_I2C_0_CLKCTRL  (0x48181564u)
#define CM_ALWON_I2C_1_CLKCTRL  (0x48181568u)

    /*
     *====================
     * Structures
     *====================
     */
/**
* \brief One line description of the structure
*
* Detailed description of the structure
*/
    typedef struct {
        volatile UINT32 I2C_REVNB_LO;                     /* 0x00 *//**< Revision ID of I2C controller */
        volatile UINT32 I2C_REVNB_HI;                     /* 0x04 *//**< Revision ID High of I2C controller */
        volatile UINT32 RSVD0[2];
        volatile UINT32 I2C_SYSC;                         /* 0x10 *//**< System configuration register */
        volatile UINT32 RSVD1[3];
        volatile UINT32 I2C_EOI;                          /* 0x20 *//**< End of Interrupt register */
        volatile UINT32 I2C_IRQSTATUS_RAW;                /* 0x24 *//**< IRQ Status Raw register */
        volatile UINT32 I2C_IRQSTATUS;                    /* 0x28 *//**< IRQ status register */
        volatile UINT32 I2C_IRQENABLE_SET;                /* 0x2C *//**< Interrupt Enable Set register */
        volatile UINT32 I2C_IRQENABLE_CLR;                /* 0x30 *//**< Interrupt Enable clear register */
        volatile UINT32 I2C_WE;                           /* 0x34 *//**< Wake up enable register */
        volatile UINT32 I2C_DMARXENABLE_SET;              /* 0x38 *//**< Receive DMA enable set register */
        volatile UINT32 I2C_DMATXENABLE_SET;              /* 0x3C *//**< Transmit DMA enable Set register */
        volatile UINT32 I2C_DMARXENABLE_CLR;              /* 0x40 *//**< Receive DMA enable Clear register */
        volatile UINT32 I2C_DMATXENABLE_CLR;              /* 0x44 *//**< Transmit DMA enable Clear register */
        volatile UINT32 I2C_DMARXWAKE_EN;                 /* 0x48 *//**< Receive DMA wake enable */
        volatile UINT32 I2C_DMATXWAKE_EN;                 /* 0x4C *//**< Transmit DMA Wake Enable */
        volatile UINT32 RSVD2[13];
        volatile UINT32 I2C_IE;                            /* 0x84 */
        volatile UINT32 I2C_STAT;                          /* 0x88 */
        volatile UINT32 RSVD3;                             /* 0x8C */
        volatile UINT32 I2C_SYSS;                         /* 0x90 *//**< System status register */
        volatile UINT32 I2C_BUF;                          /* 0x94 *//**< Buffer configuration register */
        volatile UINT32 I2C_CNT;                          /* 0x98 *//**< Count configuration register */
        volatile UINT32 I2C_DATA;                         /* 0x9C *//**< Data access register */
        volatile UINT32 RSVD4;                             /* 0xA0 */
        volatile UINT32 I2C_CON;                          /* 0xA4 *//**< Configuration register */
        volatile UINT32 I2C_OA;                           /* 0xA8 *//**< Own address configuration register */
        volatile UINT32 I2C_SA;                           /* 0xAC *//**< Slave address configuration register */
        volatile UINT32 I2C_PSC;                          /* 0xB0 *//**< Pre-Scaller configuration register */
        volatile UINT32 I2C_SCLL;                         /* 0xB4 *//**< SCL Low time configuration register */
        volatile UINT32 I2C_SCLH;                         /* 0xB8 *//**< SCL High time configuraiton register */
        volatile UINT32 I2C_SYSTEST;                      /* 0xBC *//**< System test register */
        volatile UINT32 I2C_BUFSTAT;                      /* 0xC0 *//**< Buffer Status register */
        volatile UINT32 I2C_OA1;                          /* 0xC4 *//**< Own address 1 register */
        volatile UINT32 I2C_OA2;                          /* 0xC8 *//**< Own address 2 register */
        volatile UINT32 I2C_OA3;                          /* 0xCC *//**< Own address 3 register */
        volatile UINT32 I2C_ACTOA;                        /* 0xD0 *//**< Active own address register */
        volatile UINT32 I2C_SBLOCK;                       /* 0xD4 *//**< Clock Blocking enable register */
    } __DM814X_I2C_REGS_, *DM814X_I2C_REGS;

Thanks and Regards,
Minsu Kim

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I2C time out on DM385 EVM