The TRM (SPRUH73H) in table 19-41 states the following about the UART LSR bit TXSRE when it is 1:
"Transmitter hold (TX FIFO) and shift registers are empty."
For the TXFIFOE bit set to 1 the following can be found in the same table:
"Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed."
While modifying the original LINUX driver from TI to make it switch a transceiver, I found that these two bits always seem to appear at the same time. When the drivers interrupt routine gets triggered because of THR interrupt. Both bits, TXSRE and TXFIFOE are set, though not all bits have left the shift register.
Following is a screenshot from the oscilloscope.
The yellow track is the transceiver control signal (1=TX, 0=RX) and the blue is the transmitted data (byte 0x55). The interface is configured to 115'200bps 8N0, 1 stop bit. From the image one can see that the transceiver control signal switches from TX to RX just after the start bit and 3 data bits have left the shift register. The switching from TX to RX is done when TXSRE is detected to be equal to 1.
Why is TXSRE 1 while there are still 5 bits plus the stop bit to be processed by the shift register? Polling TXSRE as suggested in http://e2e.ti.com/support/arm/sitara_arm/f/791/p/256122/896159.aspx#896159 us therefore not possible.
many thanks and kind regards, Felix