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6670 aif2 with the error of scramber seed

chenyi song
Prodigy 250 points

HI

 

Now,I use backboard to maka AIF2 of 6670 to communicate with FPGA (defined as fpga2) using link from link2 to link5 and communicate with FPGA(defined as fpga1 which is at the same board with DSP) using link0  and link1.

The platform is 8x and enable scramber seed.

The chain using link0 and link1 to communicate with fpga1 is synchronous and could transmitte data in generic mode correctly.

But ,when we use link3 to communicate with FPGA2 using backboard,the synchronous status of RX is 0x220, which is in the status of asking for ack.

According to the standard of OBSAI,after I  have transmitted  the seed, the fpga 2 could captured the seed and transfered ack,then the status machine could jump correctly.

But after I use the code make link3 to change for  link0 ,the scramber seed transmmitted by DSP can't be captuerd .

I'm confused ,could you tell me why ?

  • 0
    TI__Expert 4740 points

    Hi,

    I don't exactly understand why you couldn't capture scrambler seed from DSP for link3 but I can say you'd better connect to your two FPGA like below.

    Link0 ~ 3 to FPGA 2 ad link4,5 to FPGA 1 for generic packet, because link0 ~ 3 use the same SERDES B8 macro and link4,5 use the same SERDES B4 macro.

    We have clock phase mismatch issue when communicating between different macro. you may find more detail from 6670 Errata about this.

    you may try what I mentioned above first before further debugging scrambler seed issue.

    Regards,

    Albert

  • 0 in reply to Albert Bae
    Prodigy 250 points

     

    thanks ,

    It has been made link 0 and link1 to communicate with fpga1 and link2---link5 to communicate with fpga2 sepretely. So maybe the board can't be changed now.

    Based on this situation ,does it matter a lot ?

    In fact link0 and link1 is ok ,but link3 is not(now ,I  just use link3 only).

    In other word ,does link0 would influence on link3? In fact ,I  only aggrated link3.

    I read the errdata ,the configuration of SD and RM has been what mentioned in the article.

    according to the OBSAI ,just as the picture:

    I log the status of RX it ever jumped from wait  for seed ,and then keep waiting for ack from fpga

    now only did fpga receive the crambler seed from DSP,fpga transmiitte ack to dsp

    but ,fpga can't capture the seed ,could you tell me why?

    Enable tx ,enable scrambler ,if the clock is correct, the seed should be sent correctly ,right?

    Is there some other reason which could cause the seed not to be sent ?

    Or is there some status to show the completion  of sending seed from DSP?

     


     

  • 0 in reply to chenyi song
    TI__Expert 4740 points

    Physically, there is no difference between link0 and link3. if you see that kind of problem, you'd better check the incoming signal and clock quality by using your instruments.

    If compare the signal with link0, you may find any difference. If everything is alright, you should see the same thing from link3 that you could see from link0

    Regards,

    Albert 

  • 0 in reply to Albert Bae
    Prodigy 250 points

    ok,thanks!

    If I wanna check the status of SD,is it possible to use SD loopback?

    In fact ,I read the rxloopback and txloopback in the UG.What does is mean?

    If I wanna use loopbadk of SD,just set these two register ,is it right?

  • 0 in reply to chenyi song
    TI__Expert 4740 points

    If I wanna use loopbadk of SD,just set these two register ,is it right?

    [TI] Yes.