DM8168 VOUT1 output discrete sync YUV422 16bit data

colin he1

Intellectual 665 points

Hi everyone,

We use DVRRDK_03.50.00.05 SDK.

We Must use DM8168 VOUT1 output discrete sync YUV422 16bit data. Do not use DM8168 on chip HDMI output.

I had to some changed as follow:

1.Do not insmod ti81xxhdmi.ko(modify the load.sh and add # front insmod ./kermod/ti81xxhdmi.ko)

2.Add some Code to chang the PinMux to enable VOUT1. and changed HDMI output format

3. pContext->deviceParams[VDIS_DEV_HDMI].enable = TRUE;

pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.vencNodeNum = VDIS_VENC_HDMI;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFidPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoVsPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoHsPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoActVidPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFmt = VDIS_DVOFMT_DOUBLECHAN_DISCSYNC;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dataFormat = SYSTEM_DF_YUV422SP_UV;

Is that correct? I wonder M3 firmware may overwrite the DVO1 pinmux?

over 13 years ago

0 Brijesh Jadav over 13 years ago

TI__Guru**** 504345 points

Hi Colin,

Your changes are correct, this configres VOUT1 on 16bit discrete output. Please make sure that the pinmux settings are correct.

M3 firmware sets the pinmux at the init time, which you could overwrite it later,

Regards,

Brijesh Jadv

0 colin he1 over 13 years ago in reply to Brijesh Jadav

Intellectual 665 points

Hi Brijesh, thanks for your reply! But I find that avid(DE) sigal is not correct. My application is ti8168 vout1 output 1920X1080 to FPGA.As avid(DE) signal is wrong,so FPGA detect the resolution is not 1920X1080,but the vertical resolution 1080 is right! I find that horizontal frequency and vertical frequency are right, so I guess the AVID(DE) signal is wrong! Every time reboot ti8168, when I run my software app first time, the vout1 output is wrong,as above, but when I cancel app and run again, vout1 output is right! after that, is OK! But when reboot the ti8168, the first time to run app, vout1 output is wrong. can anyone help me?

0 Brijesh Jadav over 13 years ago in reply to colin he1

TI__Guru**** 504345 points

Hi Colin,

Could you tell what issue you are seeing the DE signal? is it toggling? how many times it is toggling?

Regards,

Brijesh Jadav

0 colin he1 over 13 years ago in reply to Brijesh Jadav

Intellectual 665 points

We use FPGA Chipscope, capture sync signal. De signal is toggling,but not sync to other signal. Likes

0 Brijesh Jadav over 13 years ago in reply to colin he1

TI__Guru**** 504345 points

Hi Colin,

DE is toggling correctly. It will not be in sync with the hs since hs signal is not hblank signal but hsync signal, It will be high for few pixels during blanking interval. so hs and de signals both are correct.

In the above diagram, hs signal is active low, so it is low for few pixels during blanking interval, you could make it active high by changing one of the sysfs entry.

Regards,

Brijesh Jadav

0 colin he1 over 13 years ago in reply to Brijesh Jadav

Intellectual 665 points

Hi Brijesh, Thanks for your reply!

TI8168 VOUT0 VOUT1 are output to FPGA, 16bit Y/C descretesync. VOUT1 output is correct(the above ), VOUT0 output is not correct(the below).

I have do this:

pContext->deviceParams[VDIS_DEV_HDMI].enable = TRUE;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.vencNodeNum = VDIS_VENC_HDMI;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFidPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoVsPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoHsPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoActVidPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFmt = VDIS_DVOFMT_DOUBLECHAN_DISCSYNC;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dataFormat = SYSTEM_DF_YUV422SP_UV;

the image sync signal is low because FPGA take a sync signal format process.

0 Brijesh Jadav over 13 years ago in reply to colin he1

TI__Guru**** 504345 points

Hi Colin,

Could you please recheck the pinmux setting for the VOU0 output?

Is it always high, never going low? If this is the case, it should be pinmux settings only causing this. If it is going low, we could check the registers settings and make sure that VOU0/1 are configured in the same way.

Regards,

Brijesh Jadav

0 colin he1 over 13 years ago in reply to Brijesh Jadav

Intellectual 665 points

Brijesh,

No, It can output high and low.but not sync to other signal.So the horizontal resolution is not right,always less than 1920.

I set pinmux as the below.

In vps_platformTI816x.c file,

static Int32 Vps_platformTI816xSetPinMux(void)
{
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0814) = 2;   //5   tsi1_dclk     vout1_b_cb_c3   VIN1_D9
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0818) = 2;   //6   tsi1_data     vout1_b_cb_c4   VIN1_D10
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x081c) = 2;   //7   tsi1_bytstrt vout1_b_cb_c5   VIN1_D11
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0820) = 2;   //8   tsi1_pacval   vout1_b_cb_c6   VIN1_D12
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0824) = 2;   //9   tsi1_pacerr   vout1_b_cb_c7   VIN1_D13
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0828) = 1;   //10 tsi2_dclk     VIN1_D14
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x082c) = 1;   //11 tsi2_data     VIN0_D20        vin0_de1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0830) = 1;   //12 tsi2_bytstrt VIN0_D21        vin0_fld1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0834) = 1;   //13 tsi2_pacval   VIN0_D22        vin0_vsync1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0838) = 1;   //14 tsi2_pacerr   VIN0_D23        vin0_hsync1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x083c) = 2;   //15 tsi3_dclk     vout1_g_y_yc6   VIN1_D4
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0840) = 2;   //16 tsi3_data     vout1_g_y_yc7   VIN1_D5
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0844) = 2;   //17 tsi3_bytstrt vout1_g_y_yc8   VIN1_D6
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0848) = 2;   //18 tsi3_pacval   vout1_g_y_yc9   VIN1_D7
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x084c) = 2;   //19 tsi3_pacerr   vout1_b_cb_c2   VIN1_D8
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0850) = 2;   //20 tsi4_dclk     vout1_hsync     VIN1_D15
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0854) = 1;   //21 tsi4_data     VIN0_D16        vin1_hsync0     vout1_fld
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0858) = 1;   //22 tsi4_bytstrt VIN0_D17        vin1_vsync0     vout1_vsync
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x085c) = 1;   //23 tsi4_pacval   VIN0_D18        vin1_fld0       vout1_b_cb_c8
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0860) = 1;   //24 tsi4_pacerr   VIN0_D19        vin1_de0        vout1_b_cb_c9
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0864) = 1;   //25 tsi5_dclk     vout0_r_cr0     vout1_b_cb_c8   vout1_clk
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0868) = 1;   //26 tsi5_data     vout0_b_cb_c0   vout1_b_cb_c9   vin1_hsync1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x086c) = 1;   //27 tsi5_bytstrt vout0_b_cb_c1   vout1_hsync     vout1_avid
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0870) = 1;   //28 tsi5_pacval   vout0_g_y_yc0   vout1_vsync     vin1_vsync1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0874) = 1;   //29 tsi5_pacerr   vout0_g_y_yc1   vout1_fld       vin1_fld1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0878) = 2;   //30 tsi6_dclk     vout1_avid      VIN1_CLK1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x087c) = 1;   //31 tsi6_data     vin0_hsync0
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0880) = 1;   //32 tsi6_bytstrt vin0_vsync0
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0884) = 1;   //33 tsi6_pacval   vin0_fld0
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0888) = 1;   //34 tsi6_pacerr   vin0_de0
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x088c) = 1;   //35 tsi7_dclk     vout0_hsync
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0890) = 1;   //36 tsi7_data     vout0_vsync
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0894) = 1;   //37 tsi7_bytstrt vout0_fld
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0898) = 1;   //38 tsi7_pacval   vout0_avid
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x089c) = 1;   //39 tsi7_pacerr   vout0_r_cr1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08b4) = 2;   //45 tso1_dclk     vout1_clk       VIN1_CLK0
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08b8) = 2;   //46 tso1_data     vout1_g_y_yc2   VIN1_D0
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08bc) = 2;   //47 tso1_bytstrt vout1_g_y_yc3   VIN1_D1
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08c0) = 2;   //48 tso1_pacval   vout1_g_y_yc4   VIN1_D2
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08c4) = 2;   //49 tso1_pacerr   vout1_g_y_yc5   VIN1_D3
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09d4) = 0;   //117 vout0_r_cr2   vout0_hsync     vout1_g_y_yc2
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09d8) = 0;   //118 vout0_r_cr3   vout0_vsync     vout1_g_y_yc3
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09dc) = 0;   //119 vout0_r_cr4   vout0_fld       vout1_g_y_yc4
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09e0) = 0;   //120 vout0_r_cr5   vout0_avid      vout1_g_y_yc5
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09e4) = 0;   //121 vout0_r_cr6   vout0_g_y_yc0   vout1_g_y_yc6
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09e8) = 0;   //122 vout0_r_cr7   vout0_g_y_yc1   vout1_g_y_yc7
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09ec) = 0;   //123 vout0_r_cr8   vout0_b_cb_c0   vout1_g_y_yc8
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09f0) = 0;   //124 vout0_r_cr9   vout0_b_cb_c1   vout1_g_y_yc9
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0C80) = 0x10;//288 iic1_scl (mode 0, pull-up selected, pull-up enabled)
    REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0C84) = 0x10;//289 iic1_sda (mode 0, pull-up selected, pull-up enabled)

// Add VOUT1 PinMux by Colin
//clk
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08B4) = 0x1;

//Y2
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08B8) = 0x1;
//Y3
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08BC) = 0x1;
//Y4
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08C0) = 0x1;
//Y5
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08C4) = 0x1;
//Y6
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x083C) = 0x1;
//Y7
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0840) = 0x1;
//Y8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0844) = 0x1;
//Y9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0848) = 0x1;
//C2
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x084C) = 0x1;
//C3
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0814) = 0x1;
//C4
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0818) = 0x1;
//C5
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x081C) = 0x1;
//C6
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0820) = 0x1;
//C7
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0824) = 0x1;
//C8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0864) = 0x2;
//C9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0868) = 0x2;

//FID
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0874) = 0x2;
//DE
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0878) = 0x1;
//HS
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x086C) = 0x2;
//VS
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0858) = 0x3;

return (FVID2_SOK);
}

0 Brijesh Jadav over 13 years ago in reply to colin he1

TI__Guru**** 504345 points

Hi Colin,

ok, Can you please take dump of 26 registers from 0x48106000 and 0x4810A000 and compare them? these should be exactly same in order to get the same output from VOUT0/1.

Rgds,

Brijesh Jadav

0 colin he1 over 13 years ago in reply to Brijesh Jadav

Intellectual 665 points

Brijesh,

When I run init.sh load.sh script.

0x48106000: 44023013
0x48106004: 00000400
0x48106008: 00000000
0x4810600c: 00000400
0x48106010: 00000000
0x48106014: 00000400
0x48106018: 00000000
0x4810601c: 184C0C77
0x48106020: 1C0C0C30
0x48106024: 1C0C0C30
0x48106028: 84465898
0x4810602c: 2C27602B
0x48106030: 2C7880BD
0x48106034: 00000464
0x48106038: 00038338
0x4810603c: 2C780118
0x48106040: 0002C000
0x48106044: 00438000
0x48106048: 05003000
0x4810604c: 05001001
0x48106050: 0024D24D
0x48106054: 2C780110
0x48106058: 0002C001
0x4810605c: 00439276
0x48106060: 05001000
0x48106064: 05008232
0x48106068: 00000000
0x4810606c: 00000000
0x48106070: 00000000
0x48106074: 00000000
0x48106078: 00000000
0x4810607c: 00000000

0x4810a000: 44033013
0x4810a004: 00000400
0x4810a008: 00000000
0x4810a00c: 00000400
0x4810a010: 00000000
0x4810a014: 00000400
0x4810a018: 00000000
0x4810a01c: 00000B00
0x4810a020: 00000B00
0x4810a024: 00000B00
0x4810a028: 84465898
0x4810a02c: 2C27602B
0x4810a030: 2C7880BD
0x4810a034: 00000464
0x4810a038: 00000000
0x4810a03c: 2C7800C0
0x4810a040: 0002C000
0x4810a044: 00438000
0x4810a048: 05003000
0x4810a04c: 05001001
0x4810a050: 0024D24D
0x4810a054: 2C7800B8
0x4810a058: 0002C001
0x4810a05c: 00439276
0x4810a060: 05001000
0x4810a064: 05008232
0x4810a068: 00000000
0x4810a06c: 00000000
0x4810a070: 00000000
0x4810a074: 00000000
0x4810a078: 00000000
0x4810a07c: 00000000

It seem something differrence.

When I run program.

0x48106000: 44043053
0x48106004: 003F0275
0x48106008: 1EA500BB
0x4810600c: 1F9901C2
0x48106010: 1FD71E67
0x48106014: 004001C2
0x48106018: 00200200
0x4810601c: 184C0C77
0x48106020: 1C0C0C30
0x48106024: 1C0C0C30
0x48106028: 84465898
0x4810602c: 2C27602B
0x48106030: 2C7880BD
0x48106034: 00000464
0x48106038: 00038338
0x4810603c: 2C7800C0
0x48106040: 0002C000
0x48106044: 00438000
0x48106048: 05003000
0x4810604c: 05001001
0x48106050: 0024D24D
0x48106054: 2C7800B8
0x48106058: 0002C001
0x4810605c: 00439276
0x48106060: 05001000
0x48106064: 05008232

0x4810a000: 44043053
0x4810a004: 003F0275
0x4810a008: 1EA500BB
0x4810a00c: 1F9901C2
0x4810a010: 1FD71E67
0x4810a014: 004001C2
0x4810a018: 00200200
0x4810a01c: 184C0C77
0x4810a020: 1C0C0C30
0x4810a024: 1C0C0C30
0x4810a028: 84465898
0x4810a02c: 2C27602B
0x4810a030: 2C7880BD
0x4810a034: 00000464
0x4810a038: 00038338
0x4810a03c: 2C7800C0
0x4810a040: 0002C000
0x4810a044: 00438000
0x4810a048: 05003000
0x4810a04c: 05001001
0x4810a050: 0024D24D
0x4810a054: 2C7800B8
0x4810a058: 0002C001
0x4810a05c: 00439276
0x4810a060: 05001000
0x4810a064: 05008232

It seem the same.

0 Brijesh Jadav over 13 years ago in reply to colin he1

TI__Guru**** 504345 points

Hi Colin,

Yes, there is no difference in configuration once you start the program. DE output should be exactly same once settings are same. Could you also dump 10 registers from 0x48100100 and share it?

Rgds,

Brijesh Jadav

0 colin he1 over 13 years ago in reply to Brijesh Jadav

Intellectual 665 points

Hi Brijesh,

OK, When I run init.sh load.sh script,

0x48100100: 01031FFF
0x48100104: 00000000
0x48100108: A0000004
0x4810010c: 40000000
0x48100110: 40000000
0x48100114: 0009010D
0x48100118: 0000000F
0x4810011c: 00000000
0x48100120: 0000000F
0x48100124: 0000000F

When I start program.

0x48100100: 01031FFF
0x48100104: 00000000
0x48100108: 30004C1E
0x4810010c: 40000000
0x48100110: 50010220
0x48100114: 000B010D
0x48100118: 0000000F
0x4810011c: 00000000
0x48100120: 00000008
0x48100124: 00000008

0 colin he1 over 13 years ago in reply to colin he1

Intellectual 665 points

I used RDK4.0.0.3, and it resolve the problem. Thanks.

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DM8168 VOUT1 output discrete sync YUV422 16bit data