interface Spartan 6 to C6678

Alex,

The solution depends on what you call high-speed.  What is your bandwidth requirement?  Any of the SERDES interfaces can be connected to an FPGA.  The faster the interface, the more expensive the FPGA and logic.  It appears that you have connected SGMII in the figures provided.  This is a reasonable simple solution.  You will need to implement an Ethernet MAC and SGMII channel in the FPGA.  These IP blocks are readily available.

You also show use of a 312.5MHz reference clock.  This is acceptable.  However, for SGMII, lower speed reference clocks are probably easier to obtain.

Tom

I think that you can not connect SGMII to GTP.

As you can see,the SGMII is LVDS signal and GTP is CML signal,they are completely different.

On the other hand,though you can connect PCIE and SRIO to spartan,it is difficult to run themat the same time,because the resourec used by the IP is so many.

You can run a SRIO/PCIE project in ISE to verify the resource.

The clock is decided by the linerate,typically the SRIO IP on Spartan 6 will use 125MHz .

Xiao,

LVDS and CML are not directly compatible.  They have similar AC swing levels but different DC bias levels.  They can be connected through an appropriate circuit.  Please refer to the Clocking Design Guide for KeyStone Devices (SPRABI4) at: http://www.ti.com/litv/pdf/sprabi4.  It discusses the AC and DC signal levels of the related standards and also shows the appropriate circuits to adapt one to the other.

Tom

^{Thank you Tom,As you said,LVDS and CML can be AC couple connected,but the SGMII signal is used as LVDS DDR mode.The GTP in Spartan 6  can not accept that mode.} 

Xiao,

SGMII is not a DDR signal.  There is no clock.  It is a SERDES interface just like SRIO or PCIe.

Tom

Thank you.

Here is a clock signal in BCM5461s,it is in DDR mode at 625MHz.So I also think that the data signal is in DDR mode.It's my fault.

Xiao,

I pulled down the CISCO SGMII spec v1.8 from the web.  It does discuss use of a 625MHz source-synchronous clock along with the 1.25GBaud data.  It refers to this as a DDR arrangement.  The data is transported over an LVDS interface in a format that supports Clock-Data Recovery (CDR) which is common in SERDES interfaces.  The spec also includes the statement:
"SGMII details source synchronous clocking; however, specific implementations may desire to recover clock from the data rather than use the supplied clock. This operation is allowed; however, all sources of data must generate the appropriate clock regardless of how they clock receive data."
This statement has been used to allow most SGMII devices to no longer supply the RX and TX clocks.  Our DSPs do not supply / support the source-synchronous clocks and they only contain RX and Tx data pairs.

Tom