Hello,
I am trying to receive a very large block of data (~2MBytes) from an FPGA via the uPP interface.
The data is being sent in 32-bit words on uPP channels A and B. My plan was to set up the uPP for
dual channel receive, single data rate and then re-combine the two received buffers in software
I set up a 50 line transfer on both channels with a 20480 byte count on DMA channels I and Q
and 20480 byte line offset. Starting target address for each transfer is aligned on an eight byte boundary
as required. I enabled the UnderFlow/OverFlow, Programming error and End-of-word interrupts. I confirmed by JTAG
that all the initializations above are being done correctly. As far as I can tell, the uPP interface and the DMA are being initialized correctly.
The issue I am having is this:
Both channels stop transferring data after the first line. I have a timer on the transfer which eventually expires. The address updates correctly
but there is no activity. I confirmed that the FPGA is still sending data. Changng the byte count and
line count has no effect (Ran into some issues at the larger byte counts as
it seems the byte count register is signed.) Both DMA status registers show current line as 2 and current byte as 0.
The only interrupt showing in the interrupt event register is the EOL interrupt which is not enabled to interrupt the CPU.
Note I am loading the DSP via JTAG and running through the transfer with a breakpoint just after. The breakpoint can be reached
after the EOW ISR sets a flag or the timer expires. If I enable EOL interrupt and set the DMAComplete Flag there everything works fine
but I need to transfer more data than can be gotten from one line.
