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AM335x with DDR2 at 266 MHz and ODT enabled

We are designing a custom board based on the BeagleBone (white).
The BeagleBone (white) has DDR2 running at 266 MHz, but uses series 33 ohm resistors instead of ODT.
The BeagleBone (white) GEL file and uboot source does NOT enable ODT.

We would like to use ODT, as recommended in the datasheet (5.6.2.2.2.9 DDR2 Signal Termination).
With ODT, no series resistors are allowed on the DQS0, DQS1, DQ0, and DQ1 net classes.

Our plan is to remove the 33 ohm resistors on the DQS0, DQS1, DQ0, and DQ1 net classes from the BeagleBone and replace them with zero ohm links.
Then I will need to enable ODT in the AM335x uboot source to allow testing of the DDR2 interface.

Please can you provide a recommended register configuration (e.g. register settings or GEL file) which works with DDR2 with ODT,
as I am not sure what register settings to use.

Also, are there any reference AM335x boards that use DDR2 with ODT? If not, why not? Power consumption perhaps?

These register looks like it needs to be modified. But I'm not sure what else.
DDR_PHY_CTRL_1 (reg_phy_rd_local_odt and/or reg_phy_wr_local_odt)?
SDRAM_CONFIG (reg_ddr_term)?

Regards,

John.

  • I mis-read the manual.

    In the BeagleBoard (white), 75 ohm ODT is enabled in the DDR2 part for writes to the DDR2 in am335x/include/asm/arch/ddr_defs.h:

    #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332

    sdram_config = MT47H128M16RT25E_EMIF_SDCFG

    But for reads from the DDR2, the ODT in the AM335x is not enabled (reg_phy_rd_local_odt in DDR_PHY_CTRL_1):

    #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005

    emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY