PCIe (C6678 + Cyclone IV GX): problem with read request

Elena Dobrynina

Other Parts Discussed in Thread: TMS320C6678

Hello all.

I need your help. I’m trying to connect a DSP (by TI) with a FPGA (by Altera) via PCI Express. A Link is established, configuration space of the remote device is available. But I can’t read/write data (outbound transaction) from/to the BAR1_0 of the FPGA. My design has the following configuration settings:

FPGA side:

Cyclone IV GX as EP

IP_Compiler for PCI Express configuration: reference clock frequency 100MHz, number of lanes x1, BAR[1:0] – 64 bit Prefetchable (PCI BAR Size: 64 Kbytes – 16 bits), BAR 2 – 32 bit Non-Prefetchable (PCI BAR Size: 32 Kbytes – 15 bits)

DSP side:

keystone TMS320C6678 as RC

Software: PCIE_exampleProject (CCS v.5.3.0, MCSDK PDK TMS320C6678 v.1.1.2.6),

PCIe reference clock 312,5 MHz (used CSL_BootCFGSetPCIEConfigPLL(0x0141);)

/* Configure Address Translation */

barCfg.location = pcie_LOCATION_LOCAL;

barCfg.mode = pcie_RC_MODE;

barCfg.base = 0x90000000;

barCfg.prefetch = pcie_BAR_NON_PREF;

barCfg.type = pcie_BAR_TYPE32;

barCfg.memSpace = pcie_BAR_MEM_MEM;

barCfg.idx = 1;

if ((retVal = Pcie_cfgBar(handle, &barCfg)) != pcie_RET_OK)

{

System_printf ("Failed to configure BAR (%d)\n", (int)retVal);

exit(1);

}

if ((retVal = pcieObTransCfg (handle, 0x70000000, 0x00000000, 0)) != pcie_RET_OK)

{

System_printf ("Failed to configure Outbound Address Translation (%d)\n", (int)retVal);

exit(1);

}

else

{

System_printf ("Successfully configured Outbound Translation!\n");

}

Configuration of the remote device:

barCfg.location = pcie_LOCATION_REMOTE;

barCfg.mode = pcie_EP_MODE;

barCfg.base = 0x70000000;

barCfg.prefetch = pcie_BAR_PREF;

barCfg.type = pcie_BAR_TYPE64;

barCfg.memSpace = pcie_BAR_MEM_MEM;

barCfg.idx = 0;

barCfg.location = pcie_LOCATION_REMOTE;

barCfg.mode = pcie_EP_MODE;

barCfg.base = 0x70010000;

barCfg.prefetch = pcie_BAR_NON_PREF;

barCfg.type = pcie_BAR_TYPE32;

barCfg.memSpace = pcie_BAR_MEM_MEM;

barCfg.idx = 2;

[C66xx_0] ************************************************

* PCIe Test Start *

* RC mode *

*********************************************************************

Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Nov 19 2012:16:03:31

Power domain is already enabled. You probably re-ran without device reset (which is OK)

PCIe Power Up.

PLL configured.

Successfully configured Inbound Translation!

Successfully configured Outbound Translation!

Starting link training...

Link is up.

---------------------------------------------------------------------

PCIESS Application register (0x21800000):

---------------------------------------------------------------------

offset 0x200: 70000001 00000000 00000000 00000000 (OB_OFFSET_INDEX0 = 0x70000000, OB_OFFSET0_HI = 0x0)

offset 0x300: 00000001 90000000 00000000 1082bd00 (IB_BAR0 = 1; IB_START0_LO = 0x90000000; IB_BAR0_HI = 0x0; IB_OFFSET0 = 0x1082bd00)

offset 0x380: 00002110 00000000 00001111 00000000

offset 0x390: 000622a0 000222a0 00000000 00000000

-------------------------------------------------------------------

PCIESS Local Config Space (0x21801000):

---------------------------------------------------------------------

offset 0x000: b005104c 00100146 04800001 00010000

offset 0x010: 00000000 90000000 00000000 00000000

offset 0x020: 00000000 00000000 00000000 00000000

offset 0x030: 00000000 00000040 00000000 000001ff

offset 0x040: 00035001 00000000 00000000 00000000

offset 0x050: 00807005 00000000 00000000 00000000

offset 0x060: 00000000 00000000 00000000 00000000

offset 0x070: 00420010 00008001 0000281f 00135422

offset 0x080: 30110008 00000040 004003c0 00000000

offset 0x090: 00000000 0000001f 00000000 00000006

offset 0x0a0: 00010002 00000000 00000000 00000000

offset 0x0b0: 00000000 00000000 00000000 00000000

offset 0x0c0: 00000000 00000000 00000000 00000000

offset 0x0d0: 00000000 00000000 00000000 00000000

offset 0x0e0: 00000000 00000000 00000000 00000000

offset 0x0f0: 00000000 00000000 00000000 00000000

offset 0x100: 00010001 00000000 00000000 00062030

offset 0x110: 00000000 00002000 000001e0 00000000

--------------------------------------------------------------------

PCIe Remote Config Space (0x21802000):

---------------------------------------------------------------------

offset 0x000: 00041172 00100000 ff000001 00000000

offset 0x010: 7000000c 00000000 70010000 00000000

offset 0x020: 00000000 00000000 00000000 00041172

offset 0x030: 00000000 00000050 00000000 00000100

offset 0x040: 00000000 02006160 00000000 00000000

offset 0x050: 00807805 00000000 00000000 00000000

offset 0x060: 00000000 00000000 00007811 00000000

offset 0x070: 00000000 00000000 00038001 00000000

offset 0x080: 00010010 00008000 00002810 0103f411

offset 0x090: 00110000 00040000 000003c0 00000000

offset 0x0a0: 00000000 00000000 00000000 00000000

offset 0x0b0: 00010001 00000000 00000000 00000000

offset 0x0c0: 00000000 00000000 00000000 00000000

offset 0x0d0: 00000000 00000000 00000000 00000000

offset 0x0e0: 00000000 00000000 00000000 00000000

offset 0x0f0: 00000000 00000000 00000000 00000000

offset 0x100: 00010002 00000000 00000001 00000000

offset 0x110: 00000000 800000ff 00000000 00000000

After link: value of DEBUG0 (0x21801728) = 0x0300E311

uint32_t *bar3remote = (uint32_t *)0x60000000;

for (i = 0x49A; i < 0x4A0; i++) {System_printf("0x60_0: %x\t", bar3remote[i]); }

TMS320C6678.ccxml:CIO:

0x60_0: 60000000 0x60_0: 20b00000 0x60_0: 60000000 0x60_0: 20b00000 0x60_0: 60000000 0x60_0: 20b00000

Kind regards,

Elena

over 12 years ago

0 Ralf Goebel over 12 years ago

Genius 3715 points

Hi Elena,

I think you also have to set the "Memory Space Enable" Bit within the Command Register of the FPGA.

Example:

{
    pcieStatusCmdReg_t statusCmd;
    pcieRegisters_t pcieRegs;

    memset (&pcieRegs, 0, sizeof(pcieRegs));
    pcieRegs.statusCmd = &statusCmd;
    Pcie_readRegs(handle, pcie_LOCATION_REMOTE, &pcieRegs);
    statusCmd.memSp  = 1;    // Enable memory decoder
    // statusCmd.busMs = 1;    // Enable bus master
    Pcie_writeRegs(handle, pcie_LOCATION_REMOTE, &pcieRegs);
}

Ralf

0 Massimiliano Bitossi over 11 years ago

Prodigy 180 points

Dear Elena,It seems that I have the same problem. Did you solve the problem just changing what Ralf told you to add in your software?

Regards,

Massimiliano

0 Elena Dobrynina over 11 years ago in reply to Massimiliano Bitossi

Prodigy 20 points

Hello, Massimiliano.

Yes, it solved the problem.

Sincerely,

Elena

0 Massimiliano Bitossi over 11 years ago in reply to Elena Dobrynina

Prodigy 180 points

Thanks Elena, I will try to see your code to understand why in my case it does not work. Howevr I have a switch between DSP and FPGA.

Regards,

Massimiliano

Processors

Processors forum

PCIe (C6678 + Cyclone IV GX): problem with read request