AM3894 GPMC_FCLK

Hi Poh,

Yes, GPMC_FCLK can be configured to run at slower speed, like for example 25MHz.

You have to modify the L3_PLL output clock to 50MHz (it is 200MHz by default). Thus the GPMC_FCLK will be 25MHz. The drawback will be that all other modules supplied by the L3_PLL will be run at that slower speed.

One of the possible ways to change the L3_PLL clock is from the linux kernel, see the below link:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

For example, I made the following modification in clock814x_data.c:

clkp = clk_get(NULL,"l3_dpll_ck");

clk_enable(clkp);

clk_set_rate(clkp, 50000000);

The clock tree for GPMC_FCLK is: osc0_clkin_ck/l3_dpll_clkin_ck/l3_dpll_ck/sysclk4_ck/sysclk6_ck/gpmc_fck

BR
Pavel

Hi Pavel,

We don't seem to find the code segment as you have indicated and what we did was instead, we added the modifications into the code.

However, after compiling the code and run, I did not able to see the change took effect by observing the pulse width of the chip select.

Anything else we could have missed out??

pb

Poh,

Yes, these three lines of code should be added in the kernel source. Here is how I modify the {EZSDK}/board-support/linux-2.6.37-pspxx.xx.xx.xx/arch/arm/mach-omap2/clock814x_data.c file:

int __init ti814x_clk_init(void)
{
    struct omap_clk *c;
    u32 cpu_clkflg = CK_TI814X;
    
      struct clk *clkp;

...................

clk_enable_init_clocks();

clkp = clk_get(NULL,"l3_dpll_ck");

clk_enable(clkp);

clk_set_rate(clkp, 50000000);

return 0;
}

Then I made new uImage and use it. And with this new uImage, I have 25MHz for the GPMC_FCLK:

root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/l3_dpll_clkin_ck/l3_dpll_ck/sysclk4_ck/sysclk6_ck/gpmc_fck# cat rate
25000000

Without these modifications, the GPMC_FCLK is 100MHz.

BR
Pavel

Hi Pavel,

Thanks for showing me on how to set it.

Unfortunately, we went through it and  I am still not seeing the effect from the oscilloscope.

I am currently setting a chip select to be around 31 FCLK wide which is about 620ns based on 50MHz FCLK. So the way I see it is that if the setting takes effect, the pulse width should be stretched to around 1.24us based on 25MHz FCLK.

Let me know if there is any other thing I should watch out for, I will monitor this thread every now and then in case you have something for me.

Thanks and regards,

poh boon

Poh,

Let me clarify something. You are measuring the GPMC_CSn[x] I/O pin with the oscilloscope, is that correct?

BR
Pavel

Poh,

Can you also measure the GPMC_CLK I/O pin, which should be equal to the GPMC_FCLK (25MHz) when GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER = 0x0.

So, what is the frequency of GPMC_CLK?

BR
Pavel

Yes, you are correct.

Unfortunately, I did not pull up this pin, so I ended up without an access point to verify the GPMC_CLK.

By the way, we are configuring the CPU GPMC to operate in asynchronous mode.

Poh,

I just saw that this question is for AM389x device. I was first thinking this is for AM387x, as we are in the DM814x/AM387x forum. These two devices (AM387x and AM389x) are similar but still have some differences.

  Please post your question in our DM816x/AM389x forum:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717.aspx

Best regards,
Pavel

Hi Pavel,

I realize the clock tree for AM3894 is different from AM387x.

clock/sys_clkin_ck/main_pll_clk4_ck/sysclk4_ck/sysclk6_ck/gpmc_fck#

Anyway, we are getting important lead based on what you have told me earlier and we are making progress.

Still want to thank you for your guidance.

Best regards,

poh boon

Hi Pavel

I am using DM3730 GPMC,now , the GPMC_FCLK is 200M, but i need it would be 50M or even slower.

I modied the code in the file:linux/arch/arm/mach-omap2/Clock34xx.c

The funciton is below :

int __init omap2_clk_set_freq(void)
{
    struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
    struct clk *dpll2_ck, *iva2_ck, *dpll3_m2_ck;
    unsigned long osc_sys_rate;
    unsigned long dsprate, l3rate;
    short err = 0 ;
    int l3div;

    /*
     * Check if any processing is required.
     */
    if ((vdd1_opp == 0) && (vdd2_opp == 0))
        return 0;

    if (WARN((vdd1_opp == 0), "VDD1 OPP is not set.\n"))
        err = 1;

    if (WARN((vdd2_opp == 0), "VDD2 OPP is not set.\n"))
        err = 1;

    /*
     * Attempt to get the required clocks
     */
    dpll1_ck = clk_get(NULL, "dpll1_ck");
    if (WARN(IS_ERR(dpll1_ck), "Failed to get dpll1_ck.\n"))
        err = 1;

    arm_fck = clk_get(NULL, "arm_fck");
    if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))
        err = 1;

    core_ck = clk_get(NULL, "core_ck");
    if (WARN(IS_ERR(core_ck), "Failed to get core_ck.\n"))
        err = 1;

    osc_sys_ck = clk_get(NULL, "osc_sys_ck");
    if (WARN(IS_ERR(osc_sys_ck), "Failed to get osc_sys_ck.\n"))
        err = 1;

    dpll2_ck = clk_get(NULL, "dpll2_ck");
    if (WARN(IS_ERR("dpll2_ck"), "Failed to get dpll2_ck.\n"))
        err = 1;

    iva2_ck = clk_get(NULL, "iva2_ck");
    if (WARN(IS_ERR("iva2_ck"), "Failed to get iva2_ck.\n"))
        err = 1;

    dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
    if (WARN(IS_ERR("dpll3_m2_ck"), "Failed to get dpll3_m2_ck.\n"))
        err = 1;

    if (err)
        return -ENOENT;

    /*
     * Set MPU frequency
     */
    mpurate = mpu_opps [vdd1_opp].rate;
    if (clk_set_rate(dpll1_ck, mpurate))
        pr_err("Unable to set MPU frequency (%u)\n", mpurate);

    /*
     * Set DSP frequency
     */
    if (omap3_has_iva()) {
        omap2_clk_iva_init_to_idle();

        dsprate = dsp_opps [vdd1_opp].rate;
        if (clk_set_rate(dpll2_ck, dsprate))
            pr_err("Unable to set DSP frequency (%lu)\n", dsprate);
    }

    /*
     * Set L3 frequency
     */
    l3div  = cm_read_mod_reg(CORE_MOD, CM_CLKSEL) &
            OMAP3430_CLKSEL_L3_MASK;

    l3rate = l3_opps[vdd2_opp].rate * l3div;

    if (clk_set_rate(dpll3_m2_ck, l3rate))
        pr_err("Unable to set L3 frequency (%lu)\n", l3rate);

    /*
     * Re-calculate the clocks
     */
    recalculate_root_clocks();

    osc_sys_rate = clk_get_rate(osc_sys_ck);

    pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
        "%ld.%01ld/%ld/%ld MHz\n",
        (osc_sys_rate / 1000000),
        ((osc_sys_rate / 100000) % 10),
        (clk_get_rate(core_ck) / 1000000),
        (clk_get_rate(arm_fck) / 1000000));

    if (omap3_has_iva()) {
        pr_info("IVA2 clocking rate: %ld MHz\n",
               (clk_get_rate(iva2_ck) / 1000000)) ;
    }

    calibrate_delay();

    return 0;
}

But now I can't change the  rate when i use the clk_set_rate() function ,

the rate can be set just 400M or 200M

I don't know the reason.can you tell me?

Hi Shuo,

This is the DM814x/AM387x forum. I am not familiar with DM3730 device. I can recommend you to ask in the DM3730 forum:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/537.aspx

Regards,
Pavel