Hello,
I need your help about a writing problem with AM335x micro processor.
I make a brief prologue to summarize aspects of the project.
I’m testing, with a BeagleBone (Rev. A6a), the reading and writing functions to interface a digital input/output card with a dedicated bus, consisting of 8 data bits, 8 address bits, and control signals CS, RD and WR.
I used address and data bus multiplexed, from the micro, and externally there is an 8 bit edged-triggered D-type flip-flops that store the address on the rising edge of ADVN_ALE.
The micro has been programmed for reading and writing functions.
The Beaglebone pins used and the related settings are shown in the following table:
|
Pin Beaglebone |
Register |
Value |
Function |
|
25 |
conf_gpmc_ad0 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
24 |
conf_gpmc_ad1 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
5 |
conf_gpmc_ad2 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
6 |
conf_gpmc_ad3 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
23 |
conf_gpmc_ad4 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
22 |
conf_gpmc_ad5 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
3 |
conf_gpmc_ad6 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
4 |
conf_gpmc_ad7 |
0x30 |
Mode=0, 0: Pullup/pulldown enabled ,1: Pullup selected , Receiver enabled |
|
26 |
conf_gpmc_csn0 |
0x08 |
Mode=0, 1: Pullup/pulldown disabled, 0: Receiver disabled |
|
7 |
conf_gpmc_advn_ale |
0x08 |
Mode=0, 1: Pullup/pulldown disabled, 0: Receiver disabled |
|
8 |
conf_gpmc_oen_ren |
0x08 |
Mode=0, 1: Pullup/pulldown disabled, 0: Receiver disabled |
|
10 |
onf_gpmc_wen |
0x08 |
Mode=0, 1: Pullup/pulldown disabled, 0: Receiver disabled |
The configuration registers settings are:
|
Register |
Value |
Function |
|
gpmc_config1 |
0x00000213 |
GPMCFCLKDIVIDER= 3, TIMEPARAGRANULARITY=×2 latencies, MUXADDDATA=Address and data multiplexed attached device, devices type= Asynchronous, size devices type= 8 bit, wait pin not monitored, Write type= Asynchronous, Read type= Asynchronous |
|
gpmc_config2 |
0x001e1e00 |
CSONTIME=0 GPMC_FCLK cycles, CSRDOFFTIME=30 GPMC_FCLK cycles, CSWROFFTIME=30 GPMC_FCLK cycles |
|
gpmc_config3 |
0x00020200 |
ADVONTIME=0 GPMC_FCLK cycle, ADVRDOFFTIME=2 GPMC_FCLK cycle, ADVWROFFTIME=2 GPMC_FCLK cycle |
|
gpmc_config4 |
0x1b041e03 |
OEONTIME=3 GPMC_FCLK cycle, OEOFFTIME=30 GPMC_FCLK cycles, WEONTIME=4 GPMC_FCLK cycle, WEOFFTIME=27 GPMC_FCLK cycles |
|
gpmc_config5 |
0x001b1e1f |
RDCYCLETIME=31 GPMC_FCLK cycles, WRCYCLETIME=30 GPMC_FCLK cycles, RDACCESSTIME=27 GPMC_FCLK cycles |
|
gpmc_config6 |
0x00000000 |
|
|
gpmc_config7 |
0x00000f41 |
BASEADDRESS=A24 in 1, CSVALID=CS enabled, MASKADDRESS=Chip-select size of 16 Mbytes |
To read I use the command: devmem2 0x01000000 b and the read value is correct whatever the configuration of the data bits
To write I use the command devmem2 0x01000000 b 0x01 but I have never seen, by the oscilloscope, the write signal (WEN) on the output pin, instead is always present read signal (OEN_REN). It performs a read instruction also when I want write.
Could you help me to find where I wrong?
I have also noticed that by changing the division of the clock GPMC_FCLK from 0 to 4, the duration of the signals CS, RD etc.. does not change and the clock remains always at 100MHz, there is the possibility of obtaining greater duration of the CS, RD etc. signals?
Thank you for your cooperation.
Best regards.
Mariano D’Angeli TELSIEL srl Piazza Salvo D’Acquisto, 13 02100 Rieti Tel.: 0746 203622 Cell.: 338 6100580 fax: 1782257759 email: mariano.dangeli@telsiel.com
