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5505 DMA I2S

Russell Barr17013
Prodigy 100 points

First thanks for the example 5505 USM_Stick_AudioFilter. It shows a good example of how to implement the I2S with ping pong buffers.

If I understand correctly how the DMA auto reload works I thing there is a small issue with the implementation. When a DMA length complete interrupt occurs the DMA channel reloads the current registers and continues the transfer. Therefore the correct data must already be in the DMA registers when the interrupt occurs. In effect then an interrupt is serviced you are setting up the next transfer that will occur not the current one.

The supplied routine work fine except when it is started. It that time it will play the same buffer is played twice. It is played first when set_dma0_ch0_Lout() is called and then again when the DMA interrupt expires and the registers are auto reloaded. This problem can easily be fixed by preloading the DMA registers with the ping pong buffer data after the DMA is started but before the DMA interrupt occurs.

Thanks again for the example.

  • 0
    Prodigy 100 points

    One other optimization question about the DMA interrupt as it is written it only services one channel per interrupt. Since all of the channels are started at the same time would not many if not all of the DMA completion interrupt also occur at the same time. Is there any reason why the DMA interrupt could not use “if” test so more than one pending channel could be serviced per interrupt instead of “if else if else if else if” than only allows one channel and forces the interrupt to stack and un-stack register on each channel being serviced.

  • 0 in reply to Russell Barr17013
    Intellectual 270 points

    Hi Russel,

    I re-implemented the same principle as in the example from scratch and used "if"instead of  "if else..."  --> it works fine. I assume that the original code would work with this modification as well, maybe you should try.

    In my implementation, I sometimes get multiple channel interrupts at the same time (according to the state of the DMA_IFR flag register when entering the ISR).

     

    Regards,

    Raphael