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debugging/understanding/analyzing cache

RCReddy
Genius 3575 points


Hi Ti Folks,

                   To understand caching deeper, I have few experiments listed and in this regard, i want to First understand what debug features are provided by L1D Cache, in other words, can i see the following

1. what cache lines are evicted,

2 which cache lines are pre-fetched

3. which cache lines are invalidated 

basically, i want to have a periodic picture of what [everything] is happening in L1D cache. 

how can i achieve above ? Assume i can print the entire L1D cache size of 32k through some mechanism, how can i make about cache operations happened w.r.t to instruction executed in DSP.

Thanks

RC Reddy

  • 0
    TI__Mastermind 21645 points

    Hi RC,

    The Cache TAG Ram Viewer might be helpful. You can open this view by going to View->Others and selecting Cache tool.

    The Cache TAG RAM view shows the set/way number, valid bit, LRU bit and Dirty bit for each line present in the cache. This should be helpful in inferring which cache line gets evicted/pre-fetched/invalidated. You can open this cache view and single step through the code  to see how the cache content changes with each instruction.

    Here's a sample screenshot showing the Cache TAG RAM view:

    Best,

    Ashish