Hello.
I'm using DM8168 on our custom board.
I confirmed the timing of the SD for evaluation.
In result, SD_CLK to SD_CMD timing was not as same as SD_CLK to SD_DATx. Please refer attached waveforms.
SD_CMD transition is near the CLK edge, so I think it did not meet the setup time.
Furthermore, delay time also thinks that it has not satisfied regulation.
We believe the timing does not seem to match the output of the DM8168.
Software environment is DVRRDK_02.00.00.24
Please tell me, if you know better countermeasures.
Incidentally, SD card is directly connect to the DM8168.
CH1:SD_CLK CH2:SD_CMD
Regards,
-okamoto