• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Subscribers 98 subscribers
  • Views 675 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interfacing IF receiver to C6670

ronengl
Intellectual 340 points

Hello,

I am looking for the best way to interface an IF receiver - ADC (150MSPS, serial LVDS/CMOS IQ data) to the C6670 DSP for RADAR signal processing.

Is there a direct way of connecting the ADC to the DSP using either SRIO or AIF2 interface (without using an  intermediate FPGA)?

If I can use AIF2, what is the best configuration to transfer pure antenna data at this rate?  

How can I take advantage of the FFTC?

Regards,

Ronen

  • 0
    TI__Mastermind 30825 points

    Ronen,

    Not unless the ADC specifically calls out SRIO or AIF2 (Antenna Interface.)  Most ADC use a serial or uPP interface and it would require glue logic, most likely from an FPGA to one of the interfaces on the C6670 to connect up to it.

    Best Regards,
    Chad 

  • 0 in reply to Chad Courtney
    Intellectual 340 points

    Hello Chad,

    Thank you for verifying this point.

    So if I use a glue logic like FPGA to transmit/recieve IQ data to/from the FFTc, what in your opinion would be the best choise for an interface, SRIO or AIF2?

    What would be the prefered way to configure the port for best performance (I have 2 input channels)?

    Best,

    Ronen

  • 0 in reply to ronengl
    TI__Mastermind 30825 points

    I'd suggest either SRIO or PCIe based on 150MSPS rate (not sure of the data size per sample but if it's say 14bit A/D w/ I & Q that's 32bits (4Byte) per sample so that's 600MB/s.  That's a bit above what the EMIF16 would give you  and SRIO and PCIe are two great common peripherals that you can get pre-built FPGA libraries to support the interfaces.  AIF2 is really specific interface for Antenna Interface traffic using the CPRI or OBSAI Antenna Interface Protocols and I'd not recommend using it for this application (unless you had an Analog Front End that used CPRI or OBSAI that is.)

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 340 points

    Thank you.

    Ronen

  • 0 in reply to Chad Courtney
    Intellectual 340 points

    Hello Chad,

    I have another question regarding the PCIe I/F on the C6670.

    Can it support a dual channel data transfer with a rate of 2.4Gbps per channel?

    Thanks,

    Ronen

  • 0 in reply to ronengl
    TI__Mastermind 30825 points

    Yes, using both lanes of PCIe it can support this.  Note that a single lane will not be able to sustain the needed data rate to support this.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 340 points

    Thanks again for your quick reply.

    Just to be absolutely clear and to make sure I understand, I need 2 independent input channels for my transceiver lets say A and B.

    Both A and B should have a data transfer rate of 2.4Gbps, total of 4.2Gbps.

    Can the PCIe supports this?

    Sorry for not being clear enough.

    Thanks,

    Ronen

  • 0 in reply to ronengl
    TI__Mastermind 30825 points

    A single lane of PCIe would not be sufficient to support this but using two lanes of PCIe would be sufficient.  I don't know what specifically you have this connected too, and thus I'm being specific that you'll need two lanes of PCIe to be able to handle the total bandwidth.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 340 points

    Thanks, got that part, I will use 2 lanes.

    I am just not completely sure that I can use 2 lanes to transfer different data on each (2.4Gbps).

    I intend to connect an FPGA to the C6670 PCIe I/ in order to transfer 2 high speed ADC channels to the DSP.

    The ADCs will be interfaced to the FPGA.

    I'm not an expert when it comes to using PCIe, so if you can elaborate on how to use the PCIe on the C6670 side for transferring 2 data channels (ingress only).

    Thanks

    Ronen

  • 0 in reply to ronengl
    TI__Mastermind 30825 points

    It's not about sending different data on each lane, and that wasn't my intent, it's about using both lanes together  to send all the data.  

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 340 points

    I understand. 

    My confusion is a result of what is written the PCIe UG (from the features section):

    "Supports a single bidirectional link interface (i.e., a single ingress port and a single

    egress port) with a maximum of two lanes width (×2)"

    "No support for using ×2 link as two ×1 links"

    Just want a confirmation on whether I can transfer different data on each of the 2 lanes.

    Thank you

    Ronen