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AM3359 (ICE) Memory Map & Boot issues

Tim Kraus
Prodigy 200 points

Other Parts Discussed in Thread: AM3359

Hello,

i'm having some trouble to understand the memory mapping and the boot procedure of the AM3359 Device on the ICE Evalboard.

1) In the Technical Reference Manual (TRM) , chapter 2.1 is the adresses 0x00000000 to 0x1FFFFFFF are named "GPMC (External Memory)", which i thought is the external NOR flash on the Board. But figure 26-3 shows that the internal ROM  is mapped starting at 0x200000. Thats confusing for me because the adresses of the two very different memorys seem to overlap?? Does anyone know what my fault is?

2) As far as i know, microproccesors always start working at 0x00000000 after power-up. There they find a branch instruction to a location where the bootloader is located. How is the powerup sequence working on the AM3359? I didn't find detailled information on this. In the TRM i read that the internal ROM contains boot code which excecutes a second bootloader in a selected memory, but how the PC gets to ROM Boot code is not clear for me!

I'm waiting for answers hopefully!
Tim

  • 0
    TI__Mastermind 44306 points

    Tim,

    I would suggest to read chapt. 26 of the TRM. This discusses the boot options fairly extensively.

    On ICE we support SPI FLASH, NOR FLASH and uSDcard booting. The EtherCAT example has different configs to showcase this.

    Regards.

  • 0
    Expert 2690 points

    Hi Tim,

    1. The boot ROM is located at 0x40020000 and not at 0x20000 (see Table 2-1 at TRM). So there is no overlap.

    2. That doesn't actually matter for you how the ARM core starts up at reset. There is no way to disable the ROM boot-loader. So from your point of view, the code is started by the ROM boot loader.

    Just for curiosity: ARM cores are configurable in silicon and can be set to start from 0xFFFF0000 instead of 0x00000000 (http://stackoverflow.com/questions/6139952/what-is-the-booting-process-for-arm). I think that's how TI implemented it and address 0xFFFF0000 contains some more ROM with "real" exception handlers table at start-up (this memory is part of reserved range).

    Best,
    Vasili

    Note: If this answer solves your question please mark post as "Answered"

  • 0 in reply to Frank Walzer
    Prodigy 200 points

    Frank Walzer said:

    I would suggest to read chapt. 26 of the TRM. This discusses the boot options fairly extensively.

    On ICE we support SPI FLASH, NOR FLASH and uSDcard booting. The EtherCAT example has different configs to showcase this.

    Thank you Frank,
    I know that - reading chapter 26 was the reason that brought up my questions.

    Vasili Galka said:

    1. The boot ROM is located at 0x40020000 and not at 0x20000 (see Table 2-1 at TRM). So there is no overlap.

    Vasili,

    thanks for your answer. I see the Boot ROM Section in the Table your wrote. But I wonder why chapter 26 doesn't mention that there is an offset of 0x4000_0000 on the 0x0002_0000...

    When I'm debugging the device and excecute a hardware reset with CCS, the PC is set to adresses like:
    0x21408        0x2140c        0x215de        0x21518        0x212ee

    I thought this is the Boot ROM?

    Vasili Galka said:

    2. That doesn't actually matter for you how the ARM core starts up at reset. There is no way to disable the ROM boot-loader. So from your point of view, the code is started by the ROM boot loader.

    Just for curiosity: ARM cores are configurable in silicon and can be set to start from 0xFFFF0000 instead of 0x00000000 (http://stackoverflow.com/questions/6139952/what-is-the-booting-process-for-arm). I think that's how TI implemented it and address 0xFFFF0000 contains some more ROM with "real" exception handlers table at start-up (this memory is part of reserved range).

    I am just interested in knowing what really happens before main() is entered. We only used really bare-metal software on non-ARM plattforms in the past for which we got a lot more information how the boot process works

  • 0 in reply to Tim Kraus
    Expert 2690 points

    Interesting... Well, if so I don't know, I'm curious too :-)

    Maybe TI have some dynamic address region remapping executed by the ROM code? i.e. ROM is mapped at 0x20000 at reset and then it is disabled and GPMC enabled? Although this sounds over complicated...

    I honestly don't think you should care much of what the ROM code does... (over what's documented at TRM ch. 26)

    Just let me point out that main() is usually not the entry point of your code. There is rather large piece of start-up code between the entry point where ROM loader jumps and main() in most cases.

  • 0 in reply to Vasili Galka
    Prodigy 200 points

    For everyone who is interested in this, the following wiki article contains some more information:

    http://processors.wiki.ti.com/index.php/AM335X_StarterWare_Booting_And_Flashing#Stages_in_SPI_Booting

    I read the the SDK Getting started guide once more. The memory starting at 0x20000 is the Application space after the bootloader in the Flash Memory