Hi,
.adpllSigmaDeltaDivider = {4,4,4,4},
is wrong, it should be
4 << CM_WKUP_CM_CLKSEL_DPLL_PERIPH_DPLL_SD_DIV_SHIFT
because this value is OR'ed unshifted into adpllConfigReg in setClkMultDiv (clock.c):
HWREG(adpllPtr->adpllConfigReg) =
(HWREG(adpllPtr->adpllConfigReg) & (~adpllPtr->adpllSigmaDeltaDividerMask)) |
adpllPtr->adpllSigmaDeltaDivider[OPPSupported];
With a dpllDivider of 23 (0x17) occupying bits 0:7 this doesn't destroy the divider value since 0x17 | 0x4 == 0x17, but it should mean that the sigma-delta divider is not configured correctly.
(We use a 19.2 MHz external clock instead of a 24 MHz clock, hence we were bitten by this.)
Thanks,
Orjan
