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The secrets of the CVDD powered for the TMSC6678??

brian feng
Prodigy 180 points
Other Parts Discussed in Thread: LM10011, TPS56121, TPS56221, LM10010

Hi Chad,

Now i am using the LM10011+TPS56121as the CVDD of the C6678.and set init voltage at 1.1V.I know DSPs will output VIDs to change its core voltage. 

I have question about it:

1. 96% DSPs output the 111111 VIDs.I think it is very curious.but the more curious is belowing.

2.most DSPs with the 1.1V core voltage work unstable.espacially the PCIE reboot.But if I change the init voltage to 1.0V or  even lower through modulating FB resistors of TPS56121.PCIE reboot will become very stable.this is not for just one DSPs.

So ,Must the init core voltage be 1.1V?by the way ,I  don't  think  I do  have understand the advantage of SmartReflex.Can you give me some advise?

Thanks very much.

Best Regards,

Brian

  • 0
    TI__Mastermind 46460 points

    Brian,

    C6678 must be used with Smart Reflex.  It is only characterized for use in this mode.  We cannot guarantee power limits or reliability without use of SR.

    The C6678 has been tuned in the fab to minimize power consumption.  This has resulted in a high percentage of the units that operate at the VID value 63 or [111111].  This is expected.  However as you have noted, this is not true for all devices.

    The PCIe issue is separate.  This behavior is not expected.  Please supply additional information about the failure.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 180 points

    Hi Tom, Thank you very much for your timely replay,and sorry for my late!

    Fristly,It's ture that not all the DSPs  operate at the VID value 63 or [111111],but the percentage is very high.you mean this is nomal?and I wonder  the rules to  define VIDS,the stability??

    Secondly,not just PCIE reboot but also PLL and SPI boot will be more stable with the lower CVDD.we have checked this not just for one C6678. 

    Thirdly,to PCIE reboot.,we have known  the re-arrangements of the PCEI packets by the RC. and we have avoided this .whtn we download programsby  the  PC .some  DSPs operat very stably,but others not : maybe deadlock with  cannot be linked with JTAG and my PC died smiutanously ;maybe run away,ect/.but when i give it a lower CVDD.it become very stable.

    I don't kown if any others encounter this problem.but it really not  fit for just one C6678.I am confused!!!

    By the way ,i replaced the TPS56121 with the TPS56221.Is it OK?Is there some disadvatages??

    Thanks again for you patience and replay!

    Best Regard!

    Brian.

  • 0 in reply to brian feng
    TI__Mastermind 46460 points

    Brian,

    Based on current silicon fab process yeilds, most C6678 devices are being programmed with a VID code of 63 or [111111].  This is expected and understood.  Parts operating with the assigned VID code programming must meet 2 criteria:  they must operate below the maximum power limit specified for the C6678 under the defined operating conditions and they must operate correctly at the maximum rated speed.

    The TPS56121 is a 15A power controller and the TPS56221 is a 25A power controller.  Both are equally sufficient to meet the required power supply needs.

    The boot issues that you are experiencing are not being seen by other customer designs.  There are C6678 designs that are running at high volumes.  You need to look into other causes such as improper power supply programming, clock rates or boot code settings.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 180 points

    Hi Tom,

    I'm still confused with the stability of the C6678 with the 1.1V CVDD.

    I checked my design caregfully! and I recover the init capcitors and resistors as noted in the PMP7256 BOM(http://www.ti.com/tool/pmp7256).The only difference is that i replace the LM10010 with the LM10011,and set the initial voltage at 1.1V.and i check the ripple waves with the chipscope.the setting is :20MHz bandwidth, ,AC coupling with 50ohm resistor. i obsrved that there are voltage sinks when the DSPs are runing programs but it is very normal when they are not  .  the wave form is belowing:

    Image 1: the waveform with the 500KHz switch frequency with running programs.

    Image 2: the waveform with the 1MHz switch frequency with running programs.


     

     

     

     

     

     

     

  • 0 in reply to brian feng
    TI__Mastermind 46460 points

    Brian,

    I do not know whether the CVDD noise is the source of the instability.  However, since you provide measurements, I will comment on this captures.  The full power supply tolerance is +/-5%.  You need to be certain that all voltage errors and noise components when measured at the load do not exceed this total.  The pictures above indicate this may be marginal in your design.  You are showing a capture with 50mv variation and this is half of the tolerance wiindow.

    You need to account for worst-case transients.  Proper bulk capacitance is needed to manage the overshoot and undershoot at worst-case transient step.  You need to use the calculators available with the TPS56221 to choose the proper supply bulk capacitors with proper ESR.  The maximum current step size is found using the Power Estimation spreadsheet for the C6678.

    The measurement was made with a 20MHz filter in the scope.  Why did you do this?  You need to be concerned with noise up to 200MHz.  All noise below this frequency must be managed by the decoupling network.  You need to measure all of the relevent noise.

    The PMP7256 design report discusses the summing of the tolerance error terms.  Please perform similar calculations and make sure that your worst-case design results in error at the BGA balls less than +/-5%.

    Tom