DM368 DDR routing topology

I'm routing a DM368 board and am trying to follow the recommended routing topology for the different net classes. However, it's proving to be difficult with the recommended orientation of the SDRAM IC (where A1 is at top-right in Figure 6-24 of the DM368 datasheet) and the memory controller to the right.

I've looked at the layout for the TMDXEVM365 evaluation module and the routing appears to be much simpler with A1 on the SDRAM at the top-left. Is there any problem with following the EVM's example? And is there anything else to be aware of ?(i.e., if they compensated this deviation from the recommendation by some other means)