Srio_allocTransmitBuffer

Hi dc,

Thanks for posting your question. Checking the DDR3 value against your cached value may be yielding incoherent data due to the cache being 'writeback'.

You can force the system to access DDR3 directly (without being able to cache the values) in 1 of 2 ways:

1. Disable cache in your system.
2. Turn off the MAR bits for DDR3 (effectively making DDR3 not cacheable). See the TMS320C66x DSP CorePac User Guide (http://www.ti.com/lit/pdf/sprugw0) for more information.

Either of these methods should cause your buffer data to be accurate when you read it out. Let us know if your issue persists or if this solves your problem.

Thanks,

Clinton

Hi dc,

I previously referenced the Multicore Shared Memory Controller (MSMC) User Guide in my post above. I meant to reference the TMS320C66x DSP CorePac User Guide. I edited the post to reflect this.

Thanks,

Clinton

HI  ClintonRodgers

thanks for your post ,I have try to turn off DDR3 cache(MAR:128~160 my ddr3 is 512Mb),but if I do that when I use "printf" it will be hung .

why is so?

i also want to use CACHE_wbLd1 function to write the data to ddr3 but I notice that the cache is 64bit align.I just want to update 4byte .

How can I achieve that?

Hi dc,

If you have further questions, knowing the following information will help us provide more insight:

1. What device are you using?
2. What vesion of CCS are you using?
3. Are you running…
   1. an example (if so, which one?)
   2. custom code based on example code (if so, based on which example? What have you modified?)
   3. custom code you wrote from scratch (if so, what resources are you referencing?)
4. Are you using an EVM or customer HW?
   1. If you're using an EVM, which one?
   2. If custom HW, did you base it off of an EVM reference?

dc jia said:

when I use "printf" it will be hung . why is so?

A "printf" requires a lot of system resources, which could be causing your program to hang. Depending on your application, you could try using a 'system_printf', which uses less resources (however it is also constrained). See the resources below for further information:

SYS/BIOS 2-Day Workshop Guide (see pg. 5-6 [pdf pg. 142]): http://software-dl.ti.com/trainingTTO/trainingTTO_public_sw/bios_2Day/BIOS_2DAY_Workshop_Student_Guide_Rev2_1.pdf

SYS/BIOS 2-Day Workshop (source of above link): http://processors.wiki.ti.com/index.php/SYS/BIOS_2-DAY_Workshop#Rev_2.0_WORKSHOP_NOW_AVAILABLE

SYS/BIOS API reference on System_printf: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_35_02_45/exports/bios_6_35_02_45/docs/cdoc/xdc/runtime/System.html#printf

SYS/BIOS API reference (source of above link): http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_35_02_45/exports/bios_6_35_02_45/docs/cdoc/index.html

E2E post about system_printf: http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/135004.aspx

Another E2E post about system_printf: http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/43747.aspx

I also wanted to point out that the suggestions to turn off the cache were not meant as optimizations. They were meant as test cases to determine if the data you are reading from the buffer and DDR is coherent. This would prove that your original data discrepancy most likely arose due to the writeback nature of the cache.

dc jia said:

i also want to use CACHE_wbLd1 function to write the data to ddr3 but I notice that the cache is 64bit align.I just want to update 4byte. How can I achieve that?

The cache line size is a parameter of the device. Referencing the C66x DSP Cache User's Guide (http://www.ti.com/lit/pdf/sprugy8 - pg. B-7), the L1D has a line size of 64 bytes.

Thanks,

Clinton