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C6678 PLL stat remains in GO

         We meet some problem for our new C6678 board.In the beginning we init the PLL:set PLLM,PLLDIV and so on,then set PLLCMD. But after that the PLLSTAT remains in "GO".

         We know the problem must come from the hardware.But now we need to wait sometime for it to be improved,we need to test some program in this situation.So I want to know:

         1. when this happen,how much the main pll output frequency is?how much the pll output to ddr/srio/hyperlink is?

         2.when this happen,is the rate of DDR/srio/hyperlink effected?Can we make DDR to 1000MHz,srio to 2.5G,hyperlink to 7.5G?

         3.when this happen,is any kind of error will occur when we use the IO interface?

          Thank you very much.

  • Yuchao,

    Are you correctly following the software steps necessary to modify the PLLDIV and PLLvalues? The GOSTAT bit in PLLSTAT must return a 0 to indicate that the GO operation has completed.

    See section 3.2.2 in http://www.ti.com/lit/ug/sprugv2f/sprugv2f.pdf

    Perform the following steps to modify PLLDIVn.
    1. Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO operation
    is currently in progress.
    2. Program the RATIO field in PLLDIVn to the desired new divide-down rate. If the
    RATIO field changed, the PLL Controller will flag the change in the
    corresponding bit of DCHANGE.
    3. Set the respective ALNn bits in ALNCTL to align any SYSCLKs after the GO
    operation.
    4. Set the GOSET bit in PLLCMD to initiate the GO operation to change the divide
    values and align the SYSCLKs as programmed.
    5. Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to indicate
    that the GO operation has completed.

    Let me know if this helps.

    Regards,

    Jayanth

  •  Jayanth

         I can make sure that the software steps to configure PLL is correctly ,because we have used it for quite a long time.It works wrong only during the time that the hardware environment is not so good.

         I have checked the steps you show me and confirmed that there is no error in software.I still wonder what will happen when we start the operation with PLL remained in GO operation.Thank you

  • Yuchao,

    It has to come out of GO operation to confirm that the GO operation is complete. The operation is undefined if it does not come out of GO.

    Are you seeing this issue with multiple devices? or is this specific to one hardware platform/device?

    Thanks,

    Jayanth

  • Jayanth

              Do you mean that the software should not do anything before it come out of GO operation? But in terms of the CSL lib of PLL init,if PLL stay in GO for a long time, the program will not wait and return a right value.Is it a bug?

              And do you think we should add the code to check the PLLSTAT ourselves after PLL init?And if it is in GO operation, we should stop the operation and exit, or continue to wait ?

  • Yuchao,

    As per the PLL User Guide (sprugv2) section 3.2.2

    Software Steps to Modify PLLDIVn Ratios
    Perform the following steps to modify PLLDIVn:
    1. Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO operation is currently in progress.
    2. Program the RATIO field in PLLDIVn to the desired new divide-down rate. If the RATIO field changed, the PLL Controller will flag the change in the corresponding bit of DCHANGE.
    3. Set the respective ALNn bits in ALNCTL to align any SYSCLKs after the GO operation.
    4. Set the GOSET bit in PLLCMD to initiate the GO operation to change the divide values and align the SYSCLKs as programmed.
    5. Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to indicate that the GO operation has completed

    Step 5 above indicates that we have to wait for GOSTAT bit in PLLSTAT returns to 0 before any other operation. Can you please reference the CSL lib where this is not being done? Thanks