DDR3 simulation issue

From other correspondence, the below clarifications were made regarding the above inquiry.

Memory Device Used : MT41J128M16JT

Software defines the IOCTRL register as below:
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
The result is the following models are used below:

For Picture 1, the following describes the waveforms shown.
The red waveform is measured at the AM3352 pin during DDR3 reading process.
The green waveform is measured at the DDR3 pin during DDR3 writing process.

BrandonAzbell said:

For Picture 1, the following describes the waveforms shown.
The red waveform is measured at the AM3352 pin during DDR3 reading process.
The green waveform is measured at the DDR3 pin during DDR3 writing process.

Is that an actual measurement on the board, or is that a simulation?

Wei Wei3 said:

The report of simulation tool shows data multi cross Vref threshold.

Can you show the output of the simulation, i.e. I don't see any kind of multi-cross in the picture you showed previously (which I presume is taken with a scope on the hardware).

Wei Wei3 said:

We’ll found the decision threshold is wrong(The blue dashes shows Vil and Vih).

Can you please elaborate?  What is the current threshold?  Where did you find it?  What do you think it should be?

1. It's a simulation.

2. This is the simulation. I also don't see any kind of multi-cross, so I think there may be something wrong with the IBIS model.

3. The current threshold shows in the picture 1. The blue dash line is the threshold. Mentor FAE tell me it's from the IBIS model of AM3352. So I think it's wrong. The right ones should show as picture 2. It's from the data sheet of Micron DDR3.

What was the blue waveform in the original picture 1?  Was that a data bit I assume?  Was that from a read or a write?  It looks like only the read was having an issue.  Are you sure we're looking at the right thing?

Wei Wei3 said:

This is the simulation. I also don't see any kind of multi-cross, so I think there may be something wrong with the IBIS model.

I don't agree with your conclusion.  Your simulation does not show any kind of multi-cross and yet it reports a multi-cross failure.  That sounds like an issue with the simulation tool (or perhaps your usage of the tool) and not an issue with the IBIS.  Perhaps we are misunderstanding the error -- I think you need some further info from the simulation tool vendor in terms of why the simulation is showing a "fail" before we can fix the issue.

Wei Wei3 said:

The current threshold shows in the picture 1. The blue dash line is the threshold. Mentor FAE tell me it's from the IBIS model of AM3352. So I think it's wrong. The right ones should show as picture 2. It's from the data sheet of Micron DDR3.

The Vih/Vil of our TI's DDR3 controller does not have to be identical to that of the DDR3 SDRAM.  In other words, the JEDEC specification is telling you the Vih/Vil values of the DDR3 itself.  The parameter that corresponds to this from the controller standpoint will actually be Voh/Vol.  In other words, when the DDR3 controller is driving data (Voh/Vol) we must make certain that the DDR3 SDRAM is seeing the correct data (Vih/Vil).  The opposite is true as well, i.e. the TI Vih/Vil levels must be compativle with the DDR3 SDRAM Voh/Vol levels.

1. It's a clock signal. I just load the waveform from the simulation data. It make no sense to the issue. I just want to see the waveform.

2. The Mentor FAE shows the simulation result of DDR3 for me during read process. I can see the Vih and Vil is the same with the JEDEC specification, so I think I can believe that the threshold is in the IBIS model of part.

3. I don't find the Vih/Vil in the AM3352 specification. Could you please give me some detailed information? We can decide whether the waveform is failed manually at first.

The Vih/Vil parameter is provided in the DDR3 section of Table 3-13 on page 91 of the AM335x Data Sheet (revision F).

Regards,
Paul