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Using BCH in GPMC NAND Controller

Glenn Sikkema
Prodigy 110 points

I am trying to use the BCH EDC engine (in 4-bit mode for the time being) that is part of the GPMC's NAND controller in the OMAP35xx series of applications processors. I am very familiar with flash memory technologies, but must confess that I'm not an expert on BCH. I see how to activate the EDC engine and generate the syndromes, but don't see in the reference manual how to correct an error that has been detected; i.e the syndromes generated when reading a page of data don't match the syndromes that were stored when that page was written. Does TI have an app note or sample code that describes how to do this?

  • 0
    Prodigy 10 points

     

    I am in the same boat.  In addition, I am trying to decipher how the OMAP35xx series boot ROM would boot from an MLC device using BCH encoding.  It looks like the ECC may be interleaved with the data area of the NAND flash, rather than all ECC placed in the NAND spare area, but it is not clear to me how this is mapped. 

    Any info would be greatly appreciated.  Even a binary dump of a bootable image would be helpful, at least then, I would have some data to test and experiment with.

    Eric Nelson