Hello,
We are trying to implement SGMII-to-SGMII connection on our custom processor board. However, I could not get it work.
The connection is between Altera Startix V FPGA and TI C6678 DSP. The connections between the chips are AC coupled with series 0.1uF capacitors. The voltage standard of the FPGA transceiver is 1.5V PCML. We know the transceiver buffers of DSP are also CML so we guess there would be no problem regarding I/O standard.
On the board, we managed to work SGMII communication between two DSPs easily. At the same time, we implemented an onboard loopback between two SGMII cores in FPGA which worked as well. But, we are not sure about the problem in DSP-to-FPGA SGMII connection.
We also checked the eye diagrams of the signals which are within the limits.
Can you tell a possible cause for the problem?
There are registers used to configure the RX and TX SGMII serdes interfaces called SGMII_SERDES_CFGRX and SGMII_SERDES_CFGTX whose values given below:
SGMII_SERDES_CFGRX = 0x00704621
SGMII_SERDES_CFGTX = 0x000108A1
We expected the malfunctioning is because of the values of the registers so we tuned them many times but none of the trials resulted with a working project.
During the trials, we did not clearly understand the function of the register named “RATE” in SGMII_SERDES_CGFTX. The FPGA does not have such a register. So, while communicating with different devices (such as FPGA), does this register play an important role or is it an internal function?
By the way, we think the issue is not related with the PLL setting of DSP since the first bit of register SGMII_SERDES_STS is zero which indicates the PLL is locked.
I appreciate your valuable comments.
Regards.
