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EMIFA_CLK not oscillating

Mary Frantz
Intellectual 580 points

Other Parts Discussed in Thread: OMAPL138

We are using a OMAPL138 with Linux on the ARM side and BIOS 5.41.10.36 on the DSP side.  We have a FPGA connected via the EMIFA bus.   We are counting on the EMIFA_CLK to run the internal logic on the FPGA.  The reads and writes to registers in the FPGA are asynchronous.   

The problem is that the EMIFA_CLK output is not toggling. It just goes high and stays there.  Looking at the PINMUX registers with the debugger on the DSP side, shows PINMUX6 = 0x00110001.   The least significant 4 bits correspond to the EMIFA_CLK pin, and a value of 1 enables the EMIFA_CLK function (according the PinMux Utility).  The OMAPL138 TRM implies that this pin is driven by the PLL once the device is released from reset.   Why aren't we seeing any output?

From the OMAPL138 Technical Reference Manual:

20.2.1 Clock Control
The EMIFA clock is output on the EMA_CLK pin and should be used when interfacing to external
memories. The EMIFA clock (EMA_CLK) does not run during device reset. When the RESET pin is
released and after the PLL controller releases the device from reset, EMA_CLK begins to oscillate at a
frequency determined by the PLL controller.
For details on clock generation and control, see the Device Clocking chapter.
The forum topic below discusses using the EMIFA_CLK as a free running clock, but does not explain how to do it:
Our hardware uses the MityDSP SOM from Critical Link.
Thanks,
Mary
  • 0
    TI__Mastermind 35645 points

    Hi Mary,

    Thanks for your post.

    I have few clarifications as below:

    1. Are you using the EMIFA internal module clock (generated by PLL controller) as reference to run the internal logic on the FPGA? or EMA_CLK signal (IO pin)?  I suggest  you to use EMA_CLK pin as a free running clock source, for your FPGA instead of using internal module clock.

    Please refer Table 20-19, 20-20, 20-21, & 20-22 in the OMAPL138 TRM as below:

    http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

    If you use EMIfA internal module clock, the following actions will occur:

    During the strobe period of a Asynchronous read operation in normal mode, on the rising edge of the clock,

    • EMA_OE rises (read operation)
    • The data on the EMA_D bus is sampled by the EMIFA

    During the strobe period of a Asynchronous write operation in normal mode, on the rising edge of the clock,

    • EMA_WE rises (write operation)
    • The EMA_WE_DQM pins deactivate

    During the strobe period of a Asynchronous read operation in Select Strobe mode, on the rising edge of the clock,

    • EMA_CS[n] (n = 2, 3, 4, or 5) and EMA_OE rise (read operation)
    • The data on the EMA_D bus is sampled by the EMIFA.

    During the strobe period of a Asynchronous write operation in Select Strobe mode, on the rising edge of the clock,

    • EMA_CS[n] (n = 2, 3, 4, or 5) and EMA_WE rise (write operation)

    In all the above cases, in both asynchronous read and write operation, the read and write signal (EMA_OE & EMA_WE) only rises.

    Note: On all the above cases, If EMA_WAIT pin is activated, the strobe period can be extended by the external device to give it more time to accept the data.

    Hope it helps!!!!!!

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 580 points

    Yes, we would like to use EMA_CLK as a free running clock source for our FPGA.  How do you achieve this?  Specifically, which registers control whether the EMA_CLK outputs a clock?  How do you configure the appropriate registers?

    I reviewed the tables you mentioned but they don't say anything about the EMA_CLK as an output.

    To be clear, we want the OMAPL138 to drive the EMA_CLK as an output.  This clock would drive the internal logic on the FPGA, which is independent of the EMIFA bus reads and writes.

    Mary

  • 0 in reply to Mary Frantz
    TI__Mastermind 35645 points

    Hi Mary,

    Thanks for your reply.

    In general, EMA_CLK pin is not needed to access asynchronous memories through EMIFA but it is needed to access synchronous memory interfaces (SDRAM/DDR2) and this pin is connected to the CLK pin of the attached SDRAM device but this pin is not necessary specific to asynchronous memory. Instead, we have EMA_A_RW pin to control EMIFA asynchronous read/write operations and this pin stays high during reads and stays low during writes.

    EMA_CLK signal toggles when interfacing to SDRAM devices but this is not really needed in case of accessing asynchronous memories through EMIFA. Still, you shall use EMA_CLK for some other functions. ( as a free running clock)

    The CPU shall program the  EMA_CLKSRC & DIV45PENA bit fields in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock source for EMIFA (Refer Sections 11.5.17 & 7.3.3( Table 7-6) in the TRM and refer the bit fields EMA_CLKSRC & DIV45PENA in Section 11.5.17).

    Thanks & regards,

    Sivaraj K

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