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Need help for MIPI DSI settings (video mode) on OMAP4460

Tim Hsu1
Prodigy 40 points
Other Parts Discussed in Thread: SYSCONFIG

Hi all,

    I'm trying to bring up a 480x800 MIPI DSI interface LCD display (video mode) on our OMAP4460 custom board, but I get a blurry screen on LCD : 

Environment :

    1. Custom omap4460 board + linux kernel 3.0.31 + android 4.0.4

    2. System clock : 38.4MHz

LCD spec. :

Maximum 500 Mbps data rate

Pixel clock cycle : 20.3 ~ 32.2 MHz 

==========================

Vertical Timings for DSI I/F

Item Symbol Condition Min. Typ. Max. Unit
Vertical cycle  VP Resolution=480x800 806 - Line
Vertical low pulse width VS  - 2 255 Line
Vertical front porch  VFP  -  2 255 Line
Vertical back porch  VBP -  2 255 Line
Vertical data start point  -  VS+VBP  4 510 Line
Vertical blanking period  VBL VS+VBP+VFP 6 765 Line
Vertical active area  - VDISP(480x800)  - 800 - Line
Vertical Refresh rate  VRR - - 60 - Hz

Horizontal Timings for DSI I/F 

Item  Symbol Condition Min. Typ. Max. Unit
HS cycle HP Resolution=480x800 504 - 1023 DCK
HS low pulse width HS 21 - 255 DCK
Horizontal back porch HBP 58 - 255 DCK
Horizontal front porch HFP 58 - 255 DCK
Horizontal data start point  HS+HBP 58 - 510 DCK
Horizontal blanking period  HBLK 137 - 765 DCK
Horizontal active area  HDISP Resolution=480x800 - 480 - DCK

==========================


My settings for MIPI DSI LCD :

static struct omap_dsi_timings wvga_lcd_dsi_timings = {
.hbp = 99,
.hfp = 70,
.hsa = 0, /* DSI_VM_TIMING1 */
.vbp = 17,
.vfp = 29,
.vsa = 4, /* DSI_VM_TIMING2 */
.vact = 800,
.tl = 894, /* DSI_VM_TIMING3 */
.hsa_hs_int = 0,
.hfp_hs_int = 0,
.hbp_hs_int = 0, /* DSI_VM_TIMING4 */
.hsa_lp_int = 0,
.hfp_lp_int = 0,
.hbp_lp_int = 2, /* DSI_VM_TIMING5 */
.bl_lp_int = 21,
.bl_hs_int = 0, /* DSI_VM_TIMING6 */
.exit_lat = 16,
.enter_lat = 16, /* DSI_VM_TIMING7 */
};

static struct omap_dss_device lcd_wvga = {
.name = "lcd",
.driver_name = "wvga_lcd",
.type = OMAP_DISPLAY_TYPE_DSI,
.phy.dsi = {
.clk_lane = 1,
.clk_pol = 0,
.data1_lane = 2,
.data1_pol = 0,
.data2_lane = 3,
.data2_pol = 0,
.data3_lane = 0,
.data3_pol = 0,
.data4_lane = 0,
.data4_pol = 0,
.type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
.line_bufs = 2,
},
.panel = {
.timings = {
.x_res = 480,
.y_res = 800,
.pixel_clock = 30396,
.hfp = 48,
.hsw = 20,
.hbp = 48,
.vfp = 29,
.vsw = 4,
.vbp = 17,
},
.acbi = 0,
.acb = 40,
.width_in_um = 75000,
.height_in_um = 130000,
},
.clocks = {
.dispc = {
.channel = {
.lck_div = 1, /* LCD */
.pck_div = 4, /* PCD */
.lcd_clk_src =
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
},
.dsi = {
.regn = 19, /* DSI_PLL_REGN */
.regm = 178, /* DSI_PLL_REGM */
.regm_dispc = 6, /* PLL_CLK1 (M4) */
.regm_dsi = 5, /* PLL_CLK2 (M5) */
.lp_clk_div = 8, /* LPDIV */
.offset_ddr_clk = 0, /* DDR PRE&DDR POST increase */
.dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
.tlpx = 0xC,
.tclk = {
.zero = 0x3B,
.prepare = 0xF,
.trail = 0x10,
},
.ths = {
.zero = 0x18,
.prepare = 0x12,
.exit = 0x21,
.trail = 0x13,
},
},
},
.ctrl = {
.pixel_size = 24,
},

.reset_gpio = 32,
.channel = OMAP_DSS_CHANNEL_LCD,
.skip_init = false,
.dsi_timings = &wvga_lcd_dsi_timings, 
};

Debug messages :

===============================

cat /d/omapdss/clk

- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck 170666666
- DISPC-CORE-CLK -
lck 170666666 lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck 119915752 lck div 1
pck 29978938 pck div 4
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck 42666666 lck div 4
pck 42666666 pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint 2021052 regn 19
CLKIN4DDR 719494512 regm 178
DSS_FCK (DSS_FCLK) 119915752 regm_dispc 6 (off)
DSI_PLL_HSDIV_DSI (PLL1_CLK2) 143898902 regm_dsi 5 (on)
- DSI1 -
dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
DSI_FCLK 143898902
DDR_CLK 179873628
TxByteClkHS 44968407
LP_CLK 8993681

===============================

cat /d/omapdss/dispc

DISPC_REVISION 00000040
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 000000a2
DISPC_IRQENABLE 0012d640
DISPC_CONTROL 00018309
DISPC_CONFIG 00020004
DISPC_CAPABLE 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_LINE_STATUS 00000197
DISPC_LINE_NUMBER 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD) 02f02f13
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD) 01101d03
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD) 00010004
DISPC_GLOBAL_ALPHA ffffffff
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD) 031f01df
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2) 00040001
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_BA0(OMAP_DSS_GFX) 10000000
DISPC_OVL_BA1(OMAP_DSS_GFX) 10000000
DISPC_OVL_POSITION(OMAP_DSS_GFX) 00000000
DISPC_OVL_SIZE(OMAP_DSS_GFX) 031f01df
DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX) 32004099
DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX) 04ff0358
DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX) 00000500
DISPC_OVL_ROW_INC(OMAP_DSS_GFX) 00007881
DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX) 00000000
DISPC_OVL_TABLE_BA(OMAP_DSS_GFX) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_PRELOAD(OMAP_DSS_GFX) 000004ff
DISPC_OVL_BA0(o) 7fa245c0
DISPC_OVL_BA1(o) 7fa245c0
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 031f01df
DISPC_OVL_ATTRIBUTES(o) 02008010
DISPC_OVL_FIFO_THRESHOLD(o) 07ff03d0
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000b81
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 031f01df
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00800000
DISPC_OVL_FIR_COEF_H(o, i) 0d7cf800
DISPC_OVL_FIR_COEF_H(o, i) 1e70f5ff
DISPC_OVL_FIR_COEF_H(o, i) 335ff5fe
DISPC_OVL_FIR_COEF_H(o, i) f74949f7
DISPC_OVL_FIR_COEF_H(o, i) f55f33fb
DISPC_OVL_FIR_COEF_H(o, i) f5701efe
DISPC_OVL_FIR_COEF_H(o, i) f87c0dff
DISPC_OVL_FIR_COEF_HV(o, i) 00800000
DISPC_OVL_FIR_COEF_HV(o, i) 037b02ff
DISPC_OVL_FIR_COEF_HV(o, i) 0c6f05fe
DISPC_OVL_FIR_COEF_HV(o, i) 205907fb
DISPC_OVL_FIR_COEF_HV(o, i) 00404000
DISPC_OVL_FIR_COEF_HV(o, i) 075920fe
DISPC_OVL_FIR_COEF_HV(o, i) 056f0cff
DISPC_OVL_FIR_COEF_HV(o, i) 027b0300
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 000007ff
DISPC_OVL_BA0(o) 7fdda000
DISPC_OVL_BA1(o) 7fdda000
DISPC_OVL_POSITION(o) 00300000
DISPC_OVL_SIZE(o) 02ef01df
DISPC_OVL_ATTRIBUTES(o) 16008018
DISPC_OVL_FIFO_THRESHOLD(o) 07ff03d0
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 02ef01df
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00800000
DISPC_OVL_FIR_COEF_H(o, i) 0d7cf800
DISPC_OVL_FIR_COEF_H(o, i) 1e70f5ff
DISPC_OVL_FIR_COEF_H(o, i) 335ff5fe
DISPC_OVL_FIR_COEF_H(o, i) f74949f7
DISPC_OVL_FIR_COEF_H(o, i) f55f33fb
DISPC_OVL_FIR_COEF_H(o, i) f5701efe
DISPC_OVL_FIR_COEF_H(o, i) f87c0dff
DISPC_OVL_FIR_COEF_HV(o, i) 00800000
DISPC_OVL_FIR_COEF_HV(o, i) 037b02ff
DISPC_OVL_FIR_COEF_HV(o, i) 0c6f05fe
DISPC_OVL_FIR_COEF_HV(o, i) 205907fb
DISPC_OVL_FIR_COEF_HV(o, i) 00404000
DISPC_OVL_FIR_COEF_HV(o, i) 075920fe
DISPC_OVL_FIR_COEF_HV(o, i) 056f0cff
DISPC_OVL_FIR_COEF_HV(o, i) 027b0300
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 000007ff
DISPC_OVL_BA0(o) 7ff3b000
DISPC_OVL_BA1(o) 7ff3b000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 002f01df
DISPC_OVL_ATTRIBUTES(o) 0a008010
DISPC_OVL_FIFO_THRESHOLD(o) 07ff03d0
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 002f01df
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00800000
DISPC_OVL_FIR_COEF_H(o, i) 0d7cf800
DISPC_OVL_FIR_COEF_H(o, i) 1e70f5ff
DISPC_OVL_FIR_COEF_H(o, i) 335ff5fe
DISPC_OVL_FIR_COEF_H(o, i) f74949f7
DISPC_OVL_FIR_COEF_H(o, i) f55f33fb
DISPC_OVL_FIR_COEF_H(o, i) f5701efe
DISPC_OVL_FIR_COEF_H(o, i) f87c0dff
DISPC_OVL_FIR_COEF_HV(o, i) 00800000
DISPC_OVL_FIR_COEF_HV(o, i) 037b02ff
DISPC_OVL_FIR_COEF_HV(o, i) 0c6f05fe
DISPC_OVL_FIR_COEF_HV(o, i) 205907fb
DISPC_OVL_FIR_COEF_HV(o, i) 00404000
DISPC_OVL_FIR_COEF_HV(o, i) 075920fe
DISPC_OVL_FIR_COEF_HV(o, i) 056f0cff
DISPC_OVL_FIR_COEF_HV(o, i) 027b0300
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 000007ff

cat /d/omapdss/dsi1_regs


DSI_REVISION 00000030
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 00000080
DSI_IRQENABLE 0015c000
DSI_CTRL 00daea99
DSI_COMPLEXIO_CFG1 6a000321
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL a0346008
DSI_TIMING1 7fff7fff
DSI_TIMING2 ffff7fff
DSI_VM_TIMING1 00046063
DSI_VM_TIMING2 04041d11
DSI_VM_TIMING3 037e0320
DSI_CLK_TIMING 00001b10
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00030000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00000000
DSI_TX_FIFO_VC_EMPTINESS 1f1f1f1f
DSI_VM_TIMING5 00000002
DSI_VM_TIMING6 00000015
DSI_VM_TIMING7 00100010
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20808791
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000004
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20808f81
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000004
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20808d81
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20808d81
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 122a1321
DSI_DSIPHY_CFG1 4206103b
DSI_DSIPHY_CFG2 b800000f
DSI_DSIPHY_CFG5 e7000000
DSI_PLL_CONTROL 00000000
DSI_PLL_STATUS 00000383
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 10a16425
DSI_PLL_CONFIGURATION2 00656008

===============================

cat /d/omapdss/dss

DSS_REVISION 00000040
DSS_SYSCONFIG 00000000
DSS_SYSSTATUS 00000001
DSS_CONTROL 00000003

===============================

Is there something wrong in my DSI/DISPC settings? How do I fix this issue?

Any assistance you can provide would be greatly appreciated.

  • 0
    TI__Genius 10965 points

    Hi Tim,

    I am not sure what might be causing the problem, but  is it me or the clock graphics on the screen ( perhaps it  is on different layer) seems quite sharp despite everything else that is blurry?

    Regards

    Boyko

  • 0 in reply to Boyko Kazakov
    Prodigy 40 points

    Hi Boyko,

       Thanks for your reply, the clock graphics looks sharper than other items on the screen. Here are more screenshots for your reference (brightness = MAX):

    ======================================================================

     ======================================================================

    Original color bar :

    ======================================================================

    ======================================================================

    As you can see, LCD has abnormal display on web browsering/color bar/applications.

    Is is possible to solve this issue by adjusting DSI/DISPC settings?

    Any assistance you can provide would be greatly appreciated.

    Tim

  • 0 in reply to Tim Hsu1
    TI__Genius 10965 points

    Tim, if it is software related the problem can always be resolved by re-timing. Are you completely sure there is no noise or  cross-talk source disrupting the DSI?

    BTW Did you try with different pixel clock frequency?

  • 0 in reply to Boyko Kazakov
    Prodigy 40 points

    Hi Boyko,

        I have tried different pixel clock frequecy but still got similar results. I am also checking our OMAP4460 custom board with hardware engineer and LCD vendor to make sure there are no hardware issues.

    Any assistance you can provide would be greatly appreciated.

    Tim

  • 0 in reply to Tim Hsu1
    Prodigy 40 points

    Hi Boyko,

        The problem has been solved by reworking hardware, thanks for your support!

    Tim