HI,
I have a customized board with AM335x. my queries are as follows
Q1) I have configured the eeprom pins as below except U9/ MCASP1_ACLKX for write control. I have tried lot of ways, but i could not do it. Could any one help me out from this situation. And also if its configured properly, how would i test it. with just these two connections i could see eeprom read write working well.
|
SL # |
AM3356ZCZA60 |
AT24C512BN-SH_ |
|||
|
ZCZ BALL NUMBER |
PIN NAME |
SIGNAL NAME |
PIN NO |
PIN NAME |
|
|
1 |
U9 |
MCASP1_ACLKX |
E2PROM_WC |
7 |
W C |
|
2 |
C17 |
UART0_CTSn |
I2C_SDA |
5 |
SDA |
|
3 |
C16 |
UART0_RTSn |
I2C_SCL |
6 |
SCL |
Q2)
The same thing holds here too... for NAND, i was not able to configure the PINS
b) for the below code (existing code with me), i could see it is configured for AD0, but how do i know its configuring U7 pin (to meet my requirements as in table). I have code for AD(x) but iam confused if it configures the right pins as in my requirements.
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);
c) i could see in my code (below). would this satisfy my write protect requirement
|
F18 |
MMC0_DAT2 |
gpio2_27 |
/* GPMC_WPN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) =
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT);
|
SL # |
AM3356ZCZA60 |
MT29F1G08ABADAWP-IT:D |
|||
|
ZCZ BALL NUMBER |
PIN NAME |
SIGNAL NAME |
PIN NO |
PIN NAME |
|
|
1 |
U7 |
GPMC_AD0 |
gpmc_ad0 |
29 |
I/O0 |
|
2 |
V7 |
GPMC_AD1 |
gpmc_ad1 |
30 |
I/O1 |
|
3 |
R8 |
GPMC_AD2 |
gpmc_ad2 |
31 |
I/O2 |
|
4 |
T8 |
GPMC_AD3 |
gpmc_ad3 |
32 |
I/O3 |
|
5 |
U8 |
GPMC_AD4 |
gpmc_ad4 |
41 |
I/O4 |
|
6 |
V8 |
GPMC_AD5 |
gpmc_ad5 |
42 |
I/O5 |
|
7 |
R9 |
GPMC_AD6 |
gpmc_ad6 |
43 |
I/O6 |
|
8 |
T9 |
GPMC_AD7 |
gpmc_ad7 |
44 |
I/O7 |
|
9 |
R7 |
GPMC_ADVn_ALE |
gpmc_advn_ale |
17 |
ALE |
|
10 |
T6 |
GPMC_BEn0_CLE |
gpmc_be0n_cle |
16 |
CLE |
|
11 |
V6 |
GPMC_CSn0 |
gpmc_csn0 |
9 |
CE# |
|
12 |
T7 |
GPMC_OEn_REn |
gpmc_oen_ren |
8 |
RE# |
|
13 |
U6 |
GPMC_WEn |
gpmc_wen |
18 |
WE# |
|
14 |
F18 |
MMC0_DAT2 |
gpio2_27 |
16 |
WP# |
Q3) for SNOR Flash (table below), i could see in my code that D0 and D1 are configured to the right PADS B17 and B16. i could also see that serial clock is connected using the below code. But how do i understd that it is referring to PAD A17 which is required for me.
HWREG(SOC_CONTROL_REGS + SPI_SCLK_CHANNEL_0) = ( ( CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE) +
GPIO_PAD_MODE_0);
|
SL # |
AM3356ZCZA60 |
N25Q128A13ESE40F |
|||
|
ZCZ BALL NUMBER |
PIN NAME |
SIGNAL NAME |
PIN NO |
PIN NAME |
|
|
1 |
V9 |
GPMC_CSn2 |
gpio1_31 |
3 |
W#/VPP/DQ2 |
|
2 |
A17 |
SPI0_SCLK |
spi0_sclk |
6 |
C |
|
3 |
A16 |
SPI0_CS0 |
spi0_cs0 |
1 |
S# |
|
4 |
B17 |
SPI0_D0 |
spi0_d0 |
5 |
DQ0 |
|
5 |
B16 |
SPI0_D1 |
spi0_d1 |
2 |
DQ1 |
And how do i configure (write a firmware code as above ) chip select for A16 and also V9 for GPMC_CSn2 (gpio1_31).
Your help is appreciated
