C6748 2 x 128-bit banking scheme

ReinierC

Good day experts,

I am in the process of learning how to write hand-optimized assembler for the C6748 DSP. I noticed in the TMS320C6000 Programmer’s Guide (spru198k.pdf) that the guide refers to selecting different memory banks and from the TMS320C674x DSP Megamodule Reference Guide (sprufk5a.pdf), the C6748 appears to have a 2 x 128-bit banking scheme.

From the TMS320C674x DSP Megamodule Reference Guide it is not immediately apparent (for me at least) how this scheme works. Can the experts please provide me with some more details, preferably with some background?

Thanks in advance!

over 12 years ago

0 Pubesh over 12 years ago

TI__Mastermind 20790 points

Reinier,

Thanks for your post.

The 2 x 128-bit banks for L2.
Kindly have a look at the below wiki page, maybe it will help you.
http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SoC_Level_Optimizations

0 Sunil Kamath over 12 years ago

TI__Expert 7470 points

Hi Reinier,

The C674x DSP has a single 256-bit memory access port to the L2 memory and as such the whole 2x128 bit L2 memory can be accessed at once. So the banking of the memory does not buy you much in this scenario if you are using L1P/D as cache - which is the recommended setup for best performance.

Regards,

Sunil

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C6748 2 x 128-bit banking scheme