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C6678 SRIO connection problem

Ming-Che Lin
Prodigy 160 points

Hi guys,

I modify C6678 SRIO example code to  connect FPGA and set line rate 1.25G on 1x mode.

The FPGA clock rate is 125MHz.

But they can not find out each other and the C6678 halt on

---> while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE);

I also modify C6670 SRIO example code to connect the same FPGA and set line rate 1.25G on 1x mode.

They can fine out each other.

The SRIO registers of C6678 are shown below:

SRIO_SERDES_STS=0x08183061                    SRIO_SERDES_CFGPLL=0x00000241                 SRIO_SERDES_CFGRX0=0x004404b5                 SRIO_SERDES_CFGTX0=0x001807b5                 SRIO_SERDES_CFGRX1=0x004404b5                 SRIO_SERDES_CFGTX1=0x001807b5                 SRIO_SERDES_CFGRX2=0x004404b5                 SRIO_SERDES_CFGTX2=0x001807b5                 SRIO_SERDES_CFGRX3=0x004404b5                 SRIO_SERDES_CFGTX3=0x001807b5                 SRIO_SP0_ERR_STAT=0x00000001                  SRIO_SP0_CTL=0x00600001                       SRIO_SP1_ERR_STAT=0x00000001                  SRIO_SP1_CTL=0x00600001                       SRIO_SP2_ERR_STAT=0x00000001                  SRIO_SP2_CTL=0x00600001                       SRIO_SP3_ERR_STAT=0x00000001                  SRIO_SP3_CTL=0x00600001                       SRIO_ERR_DET=0x00000000                       SRIO_ERR_EN=0x00000000                        SRIO_H_ADDR_CAPT=0x00000000                   SRIO_ADDR_CAPT=0x00000000                     SRIO_ID_CAPT=0x00000000                       SRIO_CTRL_CAPT=0x00000000                     SRIO_SP0_ERR_DET=0x00000000                   SRIO_SP0_RATE_EN=0x00000000                   SRIO_SP0_ERR_ATTR_CAPT_DBG0=0x00000000        SRIO_SP0_ERR_CAPT_DBG1=0x00000000             SRIO_SP0_ERR_CAPT_DBG2=0x00000000             SRIO_SP0_ERR_CAPT_DBG3=0x00000000             SRIO_SP0_ERR_CAPT_DBG4=0x00000000             SRIO_SP0_ERR_RATE=0x80000000                  SRIO_SP1_ERR_DET=0x00000000                   SRIO_SP1_RATE_EN=0x00000000                   SRIO_SP1_ERR_ATTR_CAPT_DBG0=0x00000000        SRIO_SP1_ERR_CAPT_DBG1=0x00000000             SRIO_SP1_ERR_CAPT_DBG2=0x00000000             SRIO_SP1_ERR_CAPT_DBG3=0x00000000             SRIO_SP1_ERR_CAPT_DBG4=0x00000000             SRIO_SP1_ERR_RATE=0x80000000                  SRIO_SP2_ERR_DET=0x00000000                   SRIO_SP2_RATE_EN=0x00000000                   SRIO_SP2_ERR_ATTR_CAPT_DBG0=0x00000000        SRIO_SP2_ERR_CAPT_DBG1=0x00000000             SRIO_SP2_ERR_CAPT_DBG2=0x00000000             SRIO_SP2_ERR_CAPT_DBG3=0x00000000             SRIO_SP2_ERR_CAPT_DBG4=0x00000000             SRIO_SP2_ERR_RATE=0x80000000                  SRIO_SP3_ERR_DET=0x00000000                   SRIO_SP3_RATE_EN=0x00000000                   SRIO_SP3_ERR_ATTR_CAPT_DBG0=0x00000000        SRIO_SP3_ERR_CAPT_DBG1=0x00000000             SRIO_SP3_ERR_CAPT_DBG2=0x00000000             SRIO_SP3_ERR_CAPT_DBG3=0x00000000             SRIO_SP3_ERR_CAPT_DBG4=0x00000000             SRIO_SP3_ERR_RATE=0x80000000                  SRIO_PLM_SP0_IMP_SPEC_CTL=0x00000000          SRIO_PLM_SP0_STATUS=0x00000000                SRIO_PLM_SP0_PATH_CTL=0x00000400              SRIO_PLM_SP0_DENIAL_CTL=0x30000000            SRIO_PLM_SP1_IMP_SPEC_CTL=0x00000000          SRIO_PLM_SP1_STATUS=0x00000000                SRIO_PLM_SP1_PATH_CTL=0x00000400              SRIO_PLM_SP1_DENIAL_CTL=0x30000000            SRIO_PLM_SP2_IMP_SPEC_CTL=0x00000000          SRIO_PLM_SP2_STATUS=0x00000000                SRIO_PLM_SP2_PATH_CTL=0x00000400              SRIO_PLM_SP2_DENIAL_CTL=0x30000000            SRIO_PLM_SP3_IMP_SPEC_CTL=0x00000000          SRIO_PLM_SP3_STATUS=0x00000000                SRIO_PLM_SP3_PATH_CTL=0x00000400              SRIO_PLM_SP3_DENIAL_CTL=0x30000000            SRIO_TLM_SP0_CONTROL=0x00009000               SRIO_TLM_SP0_STATUS=0x00000000                SRIO_TLM_SP0_BRR_0_CTL=0x05000000             SRIO_TLM_SP1_CONTROL=0x00009000               SRIO_TLM_SP1_STATUS=0x00000000                SRIO_TLM_SP1_BRR_0_CTL=0x05000000             SRIO_TLM_SP2_CONTROL=0x00009000               SRIO_TLM_SP2_STATUS=0x00000000                SRIO_TLM_SP2_BRR_0_CTL=0x05000000             SRIO_TLM_SP3_CONTROL=0x00009000               SRIO_TLM_SP3_STATUS=0x00000000                SRIO_TLM_SP3_BRR_0_CTL=0x05000000             SRIO_PBM_SP0_STATUS=0x00018000                SRIO_PBM_SP1_STATUS=0x00018000                SRIO_PBM_SP2_STATUS=0x00018000                SRIO_PBM_SP3_STATUS=0x00018000    

Please help me determine what might be causing the devices not to get the Port OK.

Best Regards,

Ming-Che Lin

  • 0
    TI__Genius 13235 points

    Hi Ming-Che,

    Could you answer the following questions so we can better address your problem? 

    1. Which C6678 and C6670 examples are you modifying for your application?
    2. Are you using C6678 (TMDSEVM6678) and C6670 (TMDSEVM6670) EVMs as platforms to run your code? If not, can you specify what you are using?
    3. How is the C6678 connected to the FPGA? How is the C6670 connected to the FPGA?
    4. Is the FPGA running the same firmware for both the C6670 and C6678 applications?
    5. In the register dump you provided, can you specify which registers you have modified and which registers you left unchanged from the example code. Can you provide the same information for the C6670 code you have?

    Thanks,

    Clinton