DM8148 - McBSP's Sample Rate Generator & AUXOSC Clock

Hi Gilad,

Let me start with the first question.

Gilad Z said:

1. How can I enable McBSP's Sample Rate Generator (what registers, what order)?

The McBSP registers related to the sample rate generator are: SRGR1_REG, SRGR2_REG, SPCR1_REG, SPCR2_REG and PCR_REG. For full information refer to the DM814x TRM, section 17.2.2 McBSP Sample Rate Generator.

For the programming order, refer to the DM814x TRM, section 17.2.8.2 Reset and Initialization Procedure for the Sample Rate Generator.

I will check further for your other questions.

BR
Pavel

Gilad,

Gilad Z said:

2. How can I set AUXOSC clock as its source clock  (what registers, what order)?

In case you are using the DPLL_AUDIO/sysclk20 for source to the McBSP functional clock (mcbsp_fck), you need to select:

1. OSC_SRC[24] AUDIO_PLL_SOURCE = 0x1 (source is OSC1/AUXOSC)

2. CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL = 0x0 (sysclk20)

3. McBSP_UART_CLKSRC[2:0] McBSP_CLKS_SOURCE = 0x0 (Source is CM_AUDIOCLK_MCBSP)

You can also use AUXOSC with DPLL_VIDEO0/1/HDMI/sysclk21.

See DM814x TRM, section 2.3.8 Audio PLL Clock Structure for more info.

I will check further for your other questions.

BR
Pavel

Gilad,

Gilad Z said:

3.  In the TRM, I see that SYSCLK6 can be connected to AUXOSC (by configuring the mux and DPLL_L3) and is going to the McBSP (Table 2-15).

    a. What is the purpose of SYSCLK6 in the McBSP? To where is it connected?

SYSCLK6 is the MCBSP inreface/interconnect clock - mcbsp_ick. McBSP module has two clock signals supplied from the device PRCM: functional (mcbsp_fck) and interface (mcbsp_ick). Below is an extract from the DM814x TRM:

2.3.1 Types of Clocks

The PRCM produces two types of clocks: interface and functional.

Interface clocks: these clocks primarily provide clocking for the system interconnect modules and the portions of device's functional modules which interface to the system interconnect modules. In most cases, the interface clock supplies the functional module's system interconnect interface and registers. For some modules, the interface clock is also used as functional clock. In this specification, interface clocks are represented by blue lines.

Functional clock: this clock supplies the functional part of a module or a sub-system. In some cases, a module or a subsystem may require several functional clocks: 1 or several main functional clock(s), 1 or several optional clock(s). A module needs its main clock(s) to be operational. Optional clocks are used for specific features and can be shutdown without stopping the module.

Gilad Z said:

b. Should I configure SYSCLK6 to be taken from AUXOSC?

By default sysclk6 is 100MHz. If you need to change that frequency with more precise, you can switch to the AUXOSC source.

Optionally, if DEVOSC is 20 MHz and a precise audio or video frequency is desired, a second oscillator (AUXOSC) may be utilized for video and/or audio PLLs (e.g., 27, 22.5792 MHz or other frequency between 20-30 MHz). For instance, if a precise audio reference clock is needed, AUXOSC would provide this (e.g., 22.5792 for 44.1k audio)

Gilad Z said:

c. Should I configure DPLL_L3? 

By default the DPLL_L3 output clock frequency is 200MHz. If you need different than 200MHz frequency, you can re-configure the DPLL_L3 for other frequency.

Gilad Z said:

4. In the TRM, I see that SYSCLK20 is connected to McBSP's clks input. So this mean that I need to configure the mux, DPLL_AUDIO, "/C", MCBSP_CLKSEL mux and MCBSP_CLKS_MUX?

If you want to source the McBSP functional clock (mcbsp_fck) with sysclk20, you need to configure register CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL = 0x0 (sysclk20)

Gilad Z said:

5. Should I set both PCR.SCLKME and SRGR2.CLKSM to 0? 

If you set both SCLKME and CLKSM to 0x0, the input clock for the McBSP Sample Rate Generator will be the signal on the MCBSP_CLKS pin. If you need the input clock for the McBSP Sample Rate Generator to be the mcbsp_fck, you need to set SCLKME=0 and CLKSM=1. See DM814x TRM, Table 17-9. Input Clock Selection for Sample Rate Generator.

Gilad Z said:

6. In the TRM, in McBSP's Block Diagram (Figure 17-1), it shows MCB_CLKS connected through mux to "PICLKS" input.

   "PICLKS" is not mentioned anywhere else in the manual, what is it?  What is its mux?

PICLKS is input pin of the DM814x device. The mux is controlled through the CM_AUDIOCLK_MCBSP_CLKSEL register. PICLKS can be AUD_CLKIN0 input pad, or AUD_CLKIN1 input pad, or AUD_CLKIN2 input pad or AUXOSC_XI input pad. See Figure 2-12. Audio Clock Structure.

Looking at the CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL description, this input pad source should be selected with the value of 0x3, but it is stated that this pad is tied to 0x0, thus not available.Thus you end up with the sysclk20/21/22 option.

Gilad Z said:

7. When I use McBSP's Sample Rate Generator, is CLKG (Sample Rate Generator's clock out) directly connected to MCB_CLKX

I think yes. This is an extract from the TRM:

17.2.2 McBSP Sample Rate Generator

CLKG is used as source in order to generate the output clocks CLKX/CLKR when the CLKXM/CLKRM indicates that the clock is an output. The output CLKX/CLKR is generated according to the clock polarity setting given by the CLKXP/CLKRP as follows: when falling edge, the CLKX/CLKR is CLKG inverted.

BR
Pavel

Hi Pavel,

Thank you for your answers.

First, I'll summarize my results in short:
  I. External oscillator is connected to AUXOSC clock.
 II. I've configured PLL_AUDIO, PRCM, Sample Rate Generator.
III. Result: MCB_CLKX has no clock.

I'm trying to understand what went wrong, why don't I get MCB_CLKX clock.

Refering to the answers I have more questions:

Pavel Botev said:

By default sysclk6 is 100MHz. If you need to change that frequency with more precise, you can switch to the AUXOSC source.
Optionally, if DEVOSC is 20 MHz and a precise audio or video frequency is desired, a second oscillator (AUXOSC) may be utilized for video and/or audio PLLs (e.g., 27, 22.5792 MHz or other frequency between 20-30 MHz). For instance, if a precise audio reference clock is needed, AUXOSC would provide this (e.g., 22.5792 for 44.1k audio)

Pavel Botev said:

By default the DPLL_L3 output clock frequency is 200MHz. If you need different than 200MHz frequency, you can re-configure the DPLL_L3 for other frequency.

1) a) From answer above I understand the SYSCLK6 shouldn't effect the MCB_CLKX clock, therefore I can leave it in its default value, is this correct?
b) I still don't understand: if I change SYSCLK6, what will be the influence on the system behavior?

Pavel Botev said:

1. OSC_SRC[24] AUDIO_PLL_SOURCE = 0x1 (source is OSC1/AUXOSC)
2. CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL = 0x0 (sysclk20)
3. McBSP_UART_CLKSRC[2:0] McBSP_CLKS_SOURCE = 0x0 (Source is CM_AUDIOCLK_MCBSP)

Pavel Botev said:

If you want to source the McBSP functional clock (mcbsp_fck) with sysclk20, you need to configure register CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL = 0x0 (sysclk20)

Pavel Botev said:

The McBSP registers related to the sample rate generator are: SRGR1_REG, SRGR2_REG, SPCR1_REG, SPCR2_REG and PCR_REG. For full information refer to the DM814x TRM, section 17.2.2 McBSP Sample Rate Generator.
For the programming order, refer to the DM814x TRM, section 17.2.8.2 Reset and Initialization Procedure for the Sample Rate Generator.

• SPCR2.GRST=0;
• SPCR2.XRST=0;
• SPCR1.RRST=0;
• PCR.SCLKME = 0;
• SRGR2.CLKSM = 0;
• SRGR2.CLKSM = 1;
• SRGR2.GSYNC = 1;
• SRGR1.CLKGDV = 1;
• SRGR2.FSGM = 1;
• PCR.IDLE_EN = 0;
• PCR.FSRM = 1;
• PCR.FSXM = 1;
• PCR.CLKRM = 1;
• PCR.CLKXM = 1;

Is this correct?

3) Another question is the relation between sections 17.2.8.1 and 17.2.8.2:
I start with 17.2.8.1 programming, continue with 17.2.8.2, and then do the following:

• SPCR2.GRST=1;
• Delay(); // Wait at least 2 CLKG cycles
• SPCR2.XRST=1;
• SPCR1.RRST=1;
• SPCR2.FRST=1;

Is this correct or is there a different order for programming?

Pavel Botev said:

If you set both SCLKME and CLKSM to 0x0, the input clock for the McBSP Sample Rate Generator will be the signal on the MCBSP_CLKS pin. If you need the input clock for the McBSP Sample Rate Generator to be the mcbsp_fck, you need to set SCLKME=0 and CLKSM=1. See DM814x TRM, Table 17-9. Input Clock Selection for Sample Rate Generator.

5) TRM Section “2.5 DPLLS”:
“All PLLs come up in bypass mode at reset. The software needs to program all the DPLL settings appropriately and then wait for the DPLL to be locked. Once the DPLL is locked, then DPLLs can be taken out of bypass mode.”
How do I know that the DPLL is locked? Until when should I wait? How can the DPLL be taken out of bypass mode?

6) Looking on “figure 2-19: DPLLJ Basic Structure”, the control signal of the last mux (of “clkout” signal) is not mentioned in the figure, how do I set this mux to take the upper branch (N+1 dividor, multiplier, DAC and HS1&2 branch)?

7) TRM Section “2.6.5 Modes Of Operations”:
It seems to me that I should be working in “Active & Locked” Mode (third line), what should I do to set this mode? In thie line, it mentions: “SYSRESET=0, TINITZ=1, IDLE=0”, should I set these manually? How can I set SYSRESET to 0?

8) TRM Section “2.6.6 Bypass Mode”:
What does it mean? Should it be disabled? How can it be disabled?

9) Should Mcbsp be configured to master or slave mode? how can this be done?

Thanks,

Gilad

Gilad,

Gilad Z said:

I. External oscillator is connected to AUXOSC clock.

Do you mean that you have connected external crystal to the internal auxiliary oscillator (AUXOSC)?

For this configuration, see DM814x datasheet:

7.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs

the Auxiliary (AUX) clock can optionally be used as a source for the Audio and/or Video PLLs

The DEV and AUX clocks can be sourced in two ways:
1. Using an external crystal in conjunction with the internal oscillator or
2. Using an external 1.8-V LVCMOS-compatible clock input

Note: The external crystals used with the internal oscillators must operate in fundamental parallel resonant mode only. There is no overtone support.

The AUX Clock is optional and can range from 20-30 MHz. AUX Clock can be used to source the Audio and/or Video PLLs when a very precise audio or video frequency is required.

7.4.1.1 Using the Internal Oscillators

Figure 7-8. Auxiliary Oscillator

Gilad Z said:

1) a) From answer above I understand the SYSCLK6 shouldn't effect the MCB_CLKX clock, therefore I can leave it in its default value, is this correct?

Yes, this is correct.

Gilad Z said:

b) I still don't understand: if I change SYSCLK6, what will be the influence on the system behavior?

You will have better performance, like faster McBSP registers read/write time access. But note that at OPP100 (Cortex-A8 ARM at 600MHz), the sysclk6 at 100MHz is the max value.

Gilad Z said:

2) I’ve read the section, and configured:

• SPCR2.GRST=0;
• SPCR2.XRST=0;
• SPCR1.RRST=0;
• PCR.SCLKME = 0;
• SRGR2.CLKSM = 0;
• SRGR2.CLKSM = 1;
• SRGR2.GSYNC = 1;
• SRGR1.CLKGDV = 1;
• SRGR2.FSGM = 1;
• PCR.IDLE_EN = 0;
• PCR.FSRM = 1;
• PCR.FSXM = 1;
• PCR.CLKRM = 1;
• PCR.CLKXM = 1;

Is this correct?

You want your clock tree to be the one below, right?

AUXOSC -> PLL_AUDIO -> SYSCLK20 -> McBSP module

Include the FRST in the init sequence:

• SPCR2.GRST=0;
• SPCR2.XRST=0;
• SPCR1.RRST=0;
• SPCR2.FRST=0;

• SRGR2.CLKSM = 0;  this step is not needed, please remove
• SRGR2.CLKSM = 1;

       SRGR2.GSYNC = 0;

        You need also:

        PCR.XIOEN = 0;
        PCR.FSXP=0;
        PCR.CLKXP=0;
        SRGR2.CLKSP=0;
        SPCR2.GRST=1
        SPCR1.RRST=1
        SPCR2.XRST=1
        SPCR2.FRST=1

BR
Pavel

Gilad Z said:

3) Another question is the relation between sections 17.2.8.1 and 17.2.8.2:
I start with 17.2.8.1 programming, continue with 17.2.8.2, and then do the following:

• SPCR2.GRST=1;
• Delay(); // Wait at least 2 CLKG cycles
• SPCR2.XRST=1;
• SPCR1.RRST=1;
• SPCR2.FRST=1;

Is this correct or is there a different order for programming?

I think yes.

Gilad Z said:

4) You wrote that I need to set SCLKME=0 and CLKSM=1, but looking at figure 2-12, I see that the clock goes to CLKS input at McBSP (=McBSP.CLKS external pin), therefore it seem that I need to select SCLKME=0 and CLKSM=0. What is the correct configuration?

CLKS input in figure 2-12 is NOT the McBSP.CLKS external pin. CLKS input in figure 2-12 is the McBSP module clock input, marked as PICLKS in figure 17-1.

BR
Pavel

Gilad Z said:

How do I know that the DPLL is locked?

Check the status bit <PLL>_STATUS[0] BYPASS. When 0x0 - PLL is locked, when 0x1 - PLL is in BYPASS mode.

Gilad Z said:

Until when should I wait?

Until the <PLL>_STATUS[0] BYPASS bit is equal to 0x0.

Gilad Z said:

How can the DPLL be taken out of bypass mode?

The DPLL can be taken out of bypass mode, when it is locked.

Refer to the below thread for how the DPLL is locked (taken out of bypass mode) in the u-boot source code:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/265619/936658.aspx#936658

BR
Pavel

Gilad Z said:

6) Looking on “figure 2-19: DPLLJ Basic Structure”, the control signal of the last mux (of “clkout” signal) is not mentioned in the figure, how do I set this mux to take the upper branch (N+1 dividor, multiplier, DAC and HS1&2 branch)?

This mux can not be controlled by the Software (registers settings). The path depends on the sate of the DPLL (locked or bypass). When in locked mode, the path is what you stated as desired.

Gilad Z said:

7) TRM Section “2.6.5 Modes Of Operations”:
It seems to me that I should be working in “Active & Locked” Mode (third line), what should I do to set this mode? In thie line, it mentions: “SYSRESET=0, TINITZ=1, IDLE=0”, should I set these manually? How can I set SYSRESET to 0?

To set DPLL in locked mode, refer to the e2e thread that I already provide you.

Gilad Z said:

8) TRM Section “2.6.6 Bypass Mode”:
What does it mean? Should it be disabled? How can it be disabled?

When you enter in the DPLL active&locked mode, you will leave/disable the DPLL bypass mode automatically.

Gilad Z said:

9) Should Mcbsp be configured to master or slave mode? how can this be done?

As you want to provide the functional clock from the device PRCM (sysclk20) not from outside, the MCBSP should be in master mode.

For master transmit mode, set CLKXM=1 and CLKRM=0, see table 17-8.

BR
Pavel

Gilad Z said:

III. Result: MCB_CLKX has no clock.

Make sure also pin M6 PINCNTL30[7:0] MUXMODE = 0x2 (MCB_CLKX pin)

BR
Pavel

Hi Pavel,

Thank you for your answers.

After making fixes, I now get 56 MHz clock at MCB_CLKX, but I expected to get 2.048 MHz.

My main question: 

Why do I receive 56 MHz at MCB_CLKX?

.

Additional questions:

1) I've configured DPLL_AUDIO with the following values:

• N=6
• M2=126
• M=160

Thus I expect to receive: 22.5792 * 1/(6+1)   * 160 * (1/126) = 4.096 MHz, but I receive 56 MHz.

Additionally, when I change the value of M to 170, I get the same 56 MHz.

My conclusion is that the 56 MHz clock is not coming from the DPLL_AUDIO.

Is the conclusion correct?

If not - why don't DPLL_AUDIO settings effect the clock out?

2) a) I've calculated the addresses (as seen from the dsp) as:

• CM_AUDIOCLK_MCBSP_CLKSEL.CLKSEL (CM_ALWON regs)
  PRCM (0x08180000) + CM_DPLL (0x300) + CM_AUDIOCLK_MCBSP_CLKSEL (0x88)
  Addr = 0x8180000 + 0x300 + 0x88;
• MCBSP_CLKS_MUX : MCBSP_CLKSRC.MCBSP_CLKS_SOURCE
  PLLSS (0x481C5000) + McBSP_UART_CLKSRC (0x2D8)
  Addr = 0x481C5000 + 0x2D8; 

Is this correct?

Does reading/writing to these registers pass through the mmu?

b) In the datasheet, table 2-6:

0x8180000 PRCM Peripheral Registers(C674x DSP Restricted to only exposed peripherals)

0x8183000 PRCM Support Registers(C674x DSP Restricted to only exposed peripherals)

What is the difference between peripheral and support registers?

Is CM_AUDIOCLK_MCBSP_CLKSEL peripheral or support register?

What does it mean "exposed peripherals"?

c) In the datasheet, table 2-6:

0x481C5000 PLLSS Peripheral Registers

0x481C6000 PLLSS 

What is the difference between PLLSS peripheral and PLLSS?

Is McBSP_UART_CLKSRC PLLSS peripheral register?

Can PLLSS registers can be configured only from arm (and not from dsp)? If yes - can it be done in user mode (or only kernel mode)?

3)

Pavel Botev said:

The DPLL can be taken out of bypass mode, when it is locked.

Refer to the below thread for how the DPLL is locked (taken out of bypass mode) in the u-boot source code:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/265619/936658.aspx#936658

I've configured the DPLL from the dsp during run-time, is this ok or should I configure it from kernel or during boot?

4)

Pavel Botev said:

PICLKS is input pin of the DM814x device. The mux is controlled through the CM_AUDIOCLK_MCBSP_CLKSEL register. PICLKS can be AUD_CLKIN0 input pad, or AUD_CLKIN1 input pad, or AUD_CLKIN2 input pad or AUXOSC_XI input pad. See Figure 2-12. Audio Clock Structure.

Looking at the CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL description, this input pad source should be selected with the value of 0x3, but it is stated that this pad is tied to 0x0, thus not available.Thus you end up with the sysclk20/21/22 option.

Gilad,

Note also that sysclk20 frequency can be divided down to /8 in the CM_SYSCLK20_CLKSEL[2:0] CLKSEL bitfiled.

Then you can divide the clock (max /255) before output on the MCB_CLKX pin from the SRG divider:

McBSP_SRGR1_REG[7:0] CLKGDV

I will try to provide you answers for your other questions also.

Best regards,
Pavel

Hi Pavel,

Pavel Botev said:

Gilad,

Note also that sysclk20 frequency can be divided down to /8 in the CM_SYSCLK20_CLKSEL[2:0] CLKSEL bitfiled.

Then you can divide the clock (max /255) before output on the MCB_CLKX pin from the SRG divider:

McBSP_SRGR1_REG[7:0] CLKGDV

I will try to provide you answers for your other questions also.

Best regards,
Pavel

Gilad,

Gilad Z said:

1. Why do I get 56 MHz at MCB_CLKX output?

What is the mcbsp_fck frequency you get from the PRCM? My default mcbsp_fck frequency when using EZSDK 5.05.02.00 and configure the source oscillator to be AUXOSC (22.579 MHz), is 282237500 Hz.

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck# cat rate
22579000
root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/audio_prcm1_out_ck/mcbsp_fck# cat rate
282237500

Gilad Z said:

2. Why changing DPLL_AUDIO values doesn't change the 56 MHz output?

By default the output from DPLL_AUDIO is 282237500 Hz.

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck# cat rate
282237500

DPLL_AUDIO parameters are defined in clocks_ti814x.h:

/* Put the pll config values over here */
#define AUDIO_N        19
#define AUDIO_M        500
#define AUDIO_M2      2
#define AUDIO_CLKCTRL    0x801

The formula is outclk = M/(N+1) * CLKINP * 1/M2

CLKINP is 22579000 Hz (when source is AUXOSC).

To change the DPLL_AUDIO output clock value, you need to change the N,M,M2 parameters. Then compile and build new u-boot.

Gilad Z said:

3. How to calculate CM_SYSCLK20_CLKSEL register address (I've calculated it as 0x8180000+0x300+0x50)?

No, this is not correct.

PRCM base address - 0x48180000
CM_DPLL base address - 0x0300
CM_SYSCLK20_CLKSEL offset - 0x50

Thus full address is 0x48180350

Gilad Z said:

4. Is CM_SYSCLK20_CLKSEL can be configured from dsp and at run-time?

I am not sure whether DSP can access the PRCM registers directly. I think these accesses should be done though the system MMU. See this wiki page: http://processors.wiki.ti.com/index.php/TI81XX_PSP_IOMMU_Driver_User_Guide

I will also check with the team for the DSP to PRCM access and come back to you when I have more info.

I will also check the questions from Aug 26.

Best regards,
Pavel

 Gilad,

I am not sure from where you get these 56 MHz clock at the McBSP clkx pin.

Can you share what is the frequency of your mcbsp_fck and mcbsp_ick?

As I already explain, my mcbsp_fck is 282237500 Hz, and mcbsp_ick is 100 MHz:

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/audio_prcm1_out_ck/mcbsp_fck# cat rate
282237500

root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/l3_dpll_clkin_ck/l3_dpll_ck/sysclk4_ck/sysclk6_ck/mcbsp_ick# cat rate
100000000

Gilad Z said:

1) I've configured DPLL_AUDIO with the following values:

• N=6
• M2=126
• M=160

Thus I expect to receive: 22.5792 * 1/(6+1)   * 160 * (1/126) = 4.096 MHz, but I receive 56 MHz.

Additionally, when I change the value of M to 170, I get the same 56 MHz.

My conclusion is that the 56 MHz clock is not coming from the DPLL_AUDIO.

Is the conclusion correct?

If not - why don't DPLL_AUDIO settings effect the clock out?

You can check the DPLL_AUDIO output clock frequency like below:

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck# cat rate
282237500

When I apply your settings in the u-boot/arch/arm/include/asm/arch-ti81xx/clocks_ti814x.h:

/* Put the pll config values over here */
#define AUDIO_N        6//19
#define AUDIO_M        160//500
#define AUDIO_M2    126//2
#define AUDIO_CLKCTRL    0x801

I have as result:

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck# cat rate
4095963

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/audio_prcm1_out_ck/mcbsp_fck# cat rate
4095963

Best regards,
Pavel

Gilad,

Gilad Z said:

2) a) I've calculated the addresses (as seen from the dsp) as:

• CM_AUDIOCLK_MCBSP_CLKSEL.CLKSEL (CM_ALWON regs)
  PRCM (0x08180000) + CM_DPLL (0x300) + CM_AUDIOCLK_MCBSP_CLKSEL (0x88)
  Addr = 0x8180000 + 0x300 + 0x88;
• MCBSP_CLKS_MUX : MCBSP_CLKSRC.MCBSP_CLKS_SOURCE
  PLLSS (0x481C5000) + McBSP_UART_CLKSRC (0x2D8)
  Addr = 0x481C5000 + 0x2D8; 

Is this correct?

Does reading/writing to these registers pass through the mmu?

For the CM_AUDIOCLK_MCBSP_CLKSEL, I think yes, this should be the address seen from DSP.

For the McBSP_UART_CLKSRC, as this belongs to the PLLSS, and DSP has no direct access, the read/write access should go through the system MMU. The physical address you calculated is correct. Then for DSP, this physical address should be translated to virtual by the system MMU. See DM814x TRM, section 1.5.2 MMU Integration and Figure 1-9. MMU Intergration. See also DM814x datasheet, section 2.6 DSP/EDMA Memory Management Unit (MMU)

Regards,
Pavel

Gilad,

Gilad Z said:

b) In the datasheet, table 2-6:

0x8180000 PRCM Peripheral Registers(C674x DSP Restricted to only exposed peripherals)

0x8183000 PRCM Support Registers(C674x DSP Restricted to only exposed peripherals)

What is the difference between peripheral and support registers?

Is CM_AUDIOCLK_MCBSP_CLKSEL peripheral or support register?

[/quote]

Use the Peripheral registers to configure the peripheral itself.  The support registers listed in the device Memory Map for most peripherals are interconnect registers. The support/interconnect registers are not needed by the user.

Refer to these two e2e threads:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/137233/497285.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/124109/443260.aspx

Gilad Z said:

What does it mean "exposed peripherals"?

I am not sure what is "exposed peripherals". Let me check with the team.

BR
Pavel

Gilad,

Gilad Z said:

c) In the datasheet, table 2-6:

0x481C5000 PLLSS Peripheral Registers

0x481C6000 PLLSS 

What is the difference between PLLSS peripheral and PLLSS?

Is McBSP_UART_CLKSRC PLLSS peripheral register?

Can PLLSS registers can be configured only from arm (and not from dsp)? If yes - can it be done in user mode (or only kernel mod

[/quote]

I think here PLLSS at 0x481C6000 is also related to support registers, and as I already explained, you do not need these.

I think PLLSS registers can be configured from DSP only after physical-to-virtual translation in the sys MMU. It can be done in user mode, but the PLL need first be taken out of active&locked mode to idle bypass mode.

BR
Pavel

Hi Pavel,

Is the below McBSP clk configuration to get - 4.096 MHz (ARM side) is correct (I'm using gel file)?

    GEL_TextOut("\tSet McBSP pin mux  \n","Output",1,1,1);    
    /*
     * PINCNTL30 (M6) - [7:0] 0x2 - MCB_CLKX
     *                  [17] - 0 - Pulldown (PD) selected
     *                    [16] - 0 - PU/PD enabled
     */
    *(unsigned int *)0x48140874 = 0x00002;
    
    GEL_TextOut("\tSet McBSP PLL  \n","Output",1,1,1);         
    /*
     * (PLLSS Peripheral) OSC_SRC[24] AUDIO_PLL_SOURCE = 0x1 (source is OSC1/AUXOSC)
     */
    *(unsigned int *)0x481C52C0 = 0x1000000;
    
    /*
     * (CM_DPLL) CM_SYSCLK20_CLKSEL[2:0] - 0x1 - SYSCLK_DIV_2 : Select SYS_CLK divided by 2
     * (PRCM - 0x48180000 + CM_DPLL - 0x0300 + CM_SYSCLK20_CLKSEL - 0x50)
     */
    *(unsigned int *)0x48180350 = 1;
    
    /*
     * (CM_DPLL) CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL = 0x0 - SEL1 : Select McBSP audio clock to be SYSCLK20
     */
    *(unsigned int *)0x48180388 = 0x0;
    
    /*
     * (PLLSS) McBSP_UART_CLKSRC[2:0] McBSP_CLKS_SOURCE = 0x0 (Source is CM_AUDIOCLK_MCBSP)
     */
    *(unsigned int *)0x481C52D8 = 0x0;
    
    /*
     * DPLL_AUDIO
     * 22.5792 * 1/(6+1)   * 160 * (1/126) = 4.096 MHz
     */
    /*
     * (PLLSS) AUDIOPLL_M2NDIV
     *   N - 0x06 - Pre-divider is REGN+1
     *   M2 - 0x7E (126) - Post-divider is REGM2
     */
    *(unsigned int *)0x481C5240 = 0x007E0006;
    
    /*
     * (PLLSS) AUDIOPLL_MN2DIV
     *   M2[19:16] - 0
     *   m[11:0] - 0xA0 (160)
     */
    *(unsigned int *)0x481C5244 = 0x000000A0;
    
    /*
     * (PLLSS) McBSP_UART_CLKSRC [2:0] = 0 - Source is CM_AUDIOCLK_MCBSP
     */
    *(unsigned int *)0x481C52D8 = 0;
    
    
    GEL_TextOut("\tPRCM for McBSP are in Progress, Please wait.....  \n","Output",1,1,1);         
    
    WR_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Slow Domain Peripheral*/    
    
    WR_MEM_32(CM_ALWON_MCBSP_CLKCTRL,    0x2); /*Enable McBSP Clock*/
    while(RD_MEM_32(CM_ALWON_MCBSP_CLKCTRL)!=0x2);

    while(RD_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x1100 !=0x1100);

    GEL_TextOut("\tPRCM for McBSP are Done Successfully.....  \n","Output",1,1,1);

Thanks,

HR

Hi HRi,

HRi said:

GEL_TextOut("\tSet McBSP pin mux  \n","Output",1,1,1);    
    /*
     * PINCNTL30 (M6) - [7:0] 0x2 - MCB_CLKX
     *                  [17] - 0 - Pulldown (PD) selected
     *                    [16] - 0 - PU/PD enabled
     */
    *(unsigned int *)0x48140874 = 0x00002;

The first thing I have noticed is that you are not configuring the M6 pin correctly. You are writing the value of 0x00000002 to PINCNTL30, while you should write the value of 0x000C0002. 

The reset value of PINCNTL30 is 0x000C0000.

See DM814x datasheet, Table 4-11. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions.

See also DM814x SiliconErrata:

http://www.ti.com/lit/er/sprz343c/sprz343c.pdf

Advisories 2.1.87 and 2.1.88

I will further check your other settings.

Best regards,
Pavel

HRi said:

 /*
     * DPLL_AUDIO
     * 22.5792 * 1/(6+1)   * 160 * (1/126) = 4.096 MHz
     */
    /*
     * (PLLSS) AUDIOPLL_M2NDIV
     *   N - 0x06 - Pre-divider is REGN+1
     *   M2 - 0x7E (126) - Post-divider is REGM2
     */
    *(unsigned int *)0x481C5240 = 0x007E0006;
    
    /*
     * (PLLSS) AUDIOPLL_MN2DIV
     *   M2[19:16] - 0
     *   m[11:0] - 0xA0 (160)
     */
    *(unsigned int *)0x481C5244 = 0x000000A0;

The values you load to the AUDIOPLL registers looks right, but your comment is misleading:

N2[19:16] - 0
M[11:0] - 0xA0 (160)

With the above settings, you should get 4.096 MHz out of the Audio PLL.

HRi said:

 /*
     * (CM_DPLL) CM_SYSCLK20_CLKSEL[2:0] - 0x1 - SYSCLK_DIV_2 : Select SYS_CLK divided by 2
     * (PRCM - 0x48180000 + CM_DPLL - 0x0300 + CM_SYSCLK20_CLKSEL - 0x50)
     */
    *(unsigned int *)0x48180350 = 1;

With this value (1), you will divide by 2 the Audio PLL clock, before providing it to the McBSP (4.096 / 2)! As your final goal is to provide 4.096MHz to the McBSP, set this register to 0 (4.096 / 1):

 *(unsigned int *)0x48180350 = 0;

The rest looks correct.

Best regards,
Pavel

Hi Pavel,

OK, I did the changes but still I'm not getting the correct freq. I have attached the ARM gel file (DM8148_EVM.gel) where I added McBSP_ConfigClock() function which is called by Scripts -> DM8148 Peripheral Clock Init -> McBSPClkEnable_API (I'm only using the gel file on the ARM side),

On the DSP side I'm running the function McBSP.c -> McBSP_ConfigClock (McBSP.c is attached), on the McBSP clock I'm getting 100MHz so definitely I'm doing something wrong...

0753.DM8148_EVM.gel

/**
 *  \file     mcbsp.c
 *
 *  \brief    DM8148 McBSP setting.
 */

/*
*/

#include <stdio.h>

void WriteAddr(volatile unsigned long*  Addr, volatile unsigned long  Val)
{

    *Addr = Val;
}

void McBSP_ConfigClock()
{

	/*
	 *  110h SPCR2_REG - McBSP Serial Port Control Register 2
	 *  SPCR2[6] - GRST = 0;
	 *  SPCR2[0] - XRST = 0;
	 *  SPCR2[7] - FRST = 0;
     */
     WriteAddr ((unsigned long*)0x47000110, 0);
     /*
      * 114h SPCR1_REG - McBSP Serial Port Control Register 1
      * SPCR1[0] - RRST = 0;
      */
     WriteAddr ((unsigned long*)0x47000114, 0);
     /*
      * 128h SRGR2_REG - McBSP Sample Rate Generator Register 2
      * SRGR2[13] - CLKSM = 1;
      * SRGR2[14] - CLKSP = 0;
      * SRGR2[15] - GSYNC = 0;
      */
     WriteAddr ((unsigned long*)0x47000128, 0x00002000);
     /*
      * 148h PCR_REG - McBSP Pin Control Register
      * PCR[13] - XIOEN = 0;
      * PCR[3] - FSXP = 0;
      * PCR[1] - CLKXP = 0;
      */
     WriteAddr ((unsigned long*)0x47000148, 0);
     /* 148h PCR_REG - McBSP Pin Control Register
      * PCR[9] - CLKXM = 1 - CLKX is an output pin and is driven by the internal SRG.
      *	PCR[10] - FSRM = 0 - Frame synchronization generated internally by SRG. FSR is an output pin except when GSYNC=1 in SRGR.
      *	PCR[11] - FSXM = 1 - Frame synchronization is determined by the SRG frame-synchronization mode bit FSGM in SRGR2.
      */
     WriteAddr ((unsigned long*)0x47000148, 0x00000A00);
     /*
      * 110h SPCR2_REG - McBSP Serial Port Control Register 2
      * SPCR2[6] - GRST = 1
      */
     WriteAddr ((unsigned long*)0x47000110, 0x00000040);
     /*
      * 114h SPCR1_REG - McBSP Serial Port Control Register 1
      * SPCR1[0] - RRST = 1
      */
     WriteAddr ((unsigned long*)0x47000114, 0x1);
     /*
      * 110h SPCR2_REG - McBSP Serial Port Control Register 2
      * SPCR2[0] - XRST = 1
      */
     WriteAddr ((unsigned long*)0x47000110, 0x00000041);
     /*
      * 110h SPCR2_REG - McBSP Serial Port Control Register 2
      * SPCR2[7] - FRST = 1
	  */
     WriteAddr ((unsigned long*)0x47000110, 0x000000C1);
}
/*
 * main
 */
int main(void) {
	
	printf("Start McBSP clock config\n");

	McBSP_ConfigClock();

	return 0;
}

Many thanks,

HR

Pavel,

The AUXOSC_MXI / AUX_CLKIN is 22.579MHz

Thanks,

HR

HRi,

HRi said:

On the DSP side I'm running the function McBSP.c -> McBSP_ConfigClock (McBSP.c is attached), on the McBSP clock I'm getting 100MHz so definitely I'm doing something wrong...

How do you measure this 100MHz clock on MCB_CLKX pin, is it with an oscilloscope?

Can you try to run everything from A8, without switching to DSP core. Do you have the same result?

BR
Pavel

Hi Pavel,

Yes, with oscilloscope, OK will try it,Have you had the chance to review the files and see if anything is wrong? can you try to run them?

Is there a away to read the PLL frequencies? so I can see if the configuration is correct,

Thanks,

HR

HRi,

HRi said:

Have you had the chance to review the files and see if anything is wrong? can you try to run them?

Sorry, I am busy with other tasks. I will run them at later stage.

HRi said:

Is there a away to read the PLL frequencies? so I can see if the configuration is correct,

You can export the Audio PLL clock output to the clkout0/1 device pin, see DM814x TRM, section 2.3.11 Clock Output Pin. You can export to clkout0 or clkout1 pin. You need to configure the following registers:

CM_CLKOUT_CTRL[1:0] CLKOUTSOURCE = 0x3 (Audio PLL clock)
                              [5:3] CLKOUTDIV = 0x0
                              [7] CLKOUTEN = 0x1

CLKOUT_MUX[3:0] CLKOUT0_MUX = 0x0 (for clkout0 pin)
                      [19:16] CLKOUT1_MUX = 0x0 (for clkout1 pin)

PINCNTL134[7:0] MUXMODE = 0x20 (CLKOUT0)
PINCNTL259[7:0] MUXMODE = 0x4 (CLKOUT0)
PINCNTL127[7:0] MUXMODE = 0x10 (CLKOUT1)
PINCNTL152[7:0] MUXMODE = 0x20 (CLKOUT1)

Other thing you can check is how the Audio PLL is configured in the GEL file provided with the EZSDK 5.05.02.00:

ti-ezsdk_dm814x-evm_5_05_02_00/board-support/host-tools/DM814x_gel.zip/DM814x_PG2.x.gel

PLL_SETUP() {

cmdAUDIOPLL(CLKIN,19,800,4);

}

cmdAUDIOPLL(int CLKIN,int N, int M, int M2)
{
        DCOCLK_COMP(CLKIN,N,M);
        if(HSMODE == 2){   
            PLL_Clocks_Config(AUDIO_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2);
            GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
        }
        else if (HSMODE == 1){
            PLL_Clocks_Config(AUDIO_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1);  
             GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
        }
        else {
                  GEL_TextOut("\t AUDIO PLL NOT Configured.Wrong DCOCLK Output\n");
        }
 
}

PLL_Clocks_Config(UWORD32 Base_Address,UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2,UWORD32 CLKCTRL_VAL)
{
    UWORD32 m2nval,mn2val,read_clkctrl,clk_out,ref_clk,clkout_dco = 0;
    m2nval = (M2<<16) | N;
    mn2val =  M;
    ref_clk     = CLKIN/(N+1);
    clkout_dco  = ref_clk*M;
    clk_out     = clkout_dco/M2;
    WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)|0x00800000);
    while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000101) != 0x00000101);
    WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)& 0xfffffffe);
    wait_delay(3);
    WR_MEM_32((Base_Address+M2NDIV    ),m2nval);
    WR_MEM_32((Base_Address+MN2DIV    ),mn2val);
    wait_delay(3);
    WR_MEM_32((Base_Address+TENABLEDIV),0x1);
    wait_delay(3);
    WR_MEM_32((Base_Address+TENABLEDIV),0x0);
    wait_delay(3);
    WR_MEM_32((Base_Address+TENABLE   ),0x1);
    wait_delay(3);
    WR_MEM_32((Base_Address+TENABLE   ),0x0);
    wait_delay(3);
    read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
    //configure the TINITZ(bit0) and CLKDCO BITS IF REQUIRED
    WR_MEM_32(Base_Address+CLKCTRL,(read_clkctrl & 0xff7fe3ff) | CLKCTRL_VAL);
    read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
    // poll for the freq,phase lock to occur
    while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000600) != 0x00000600);
    //wait fot the clocks to get stabized
    wait_delay(10);
    CLKOUT    = clk_out;
}

The result clock output value is printed (200MHz default value):

CortexA8: GEL Output:      AUDIO ADPLLJ CLKOUT  value is  = 200

Best regards,
Pavel

Hi Pavel,

OK, Please note that in the gel file I'm already using the cmdAUDIOPLL function to configure the PLL,

Many Thanks,

HR

Hi Pavel,

We tried to run everyting on the ARM side with no successes, We already tried to route the Audio clock to clkout0 but we don't see anything,

The clock routing is -

        /*
         * (PRCM - 0x48180000 + CM_DEVICE - 0x0100 + CM_CLKOUT_CTRL - 0x0)
         * CM_CLKOUT_CTRL[1:0] - CLKOUTSOURCE = 0x3 (Audio PLL clock)
         * CM_CLKOUT_CTRL[5:3] - CLKOUTDIV = 0x0
         * CM_CLKOUT_CTRL[7] - CLKOUTEN = 0x1
         */
        *(unsigned int *)0x48180100 = 0x00000083;
        /*
         *  2E4h CLKOUT_MUX
         * (PLLSS Peripheral) CLKOUT_MUX[3:0] - CLKOUT0_MUX = 0x0 (Source is PRCM_SYSCLK_OUT)
         * (PLLSS Peripheral) CLKOUT_MUX[19:16] - CLKOUT1_MUX = 0x0 (Source is PRCM_SYSCLK_OUT)
         */
        *(unsigned int *)0x481C52E4 = 0x0000000;
        /*
         * AE17 - PINCNTL134[7:0] MUXMODE = 0x20 (CLKOUT0)
         */
        *(unsigned int *)0x48140A14 = 0x000C0020;

The McBSP clock is -

    GEL_TextOut("\tSet McBSP pin mux  \n","Output",1,1,1);    
    /*
     * PINCNTL30 (M6) - [7:0] 0x2 - MCB_CLKX
     *                  [17] - 0 - Pulldown (PD) selected
     *                    [16] - 0 - PU/PD enabled
     */
    *(unsigned int *)0x48140874 = 0x000C0002;
    
    GEL_TextOut("\tSet McBSP PLL  \n","Output",1,1,1);         
    /*
     * (PLLSS Peripheral) OSC_SRC[24] AUDIO_PLL_SOURCE = 0x1 (source is OSC1/AUXOSC)
     */
    *(unsigned int *)0x481C52C0 = 0x1000000;
    
    /*
     * (CM_DPLL) CM_SYSCLK20_CLKSEL[2:0] - 0x0 - SYSCLK_DIV_1 : Select SYS_CLK divided by 1
     * (PRCM - 0x48180000 + CM_DPLL - 0x0300 + CM_SYSCLK20_CLKSEL - 0x50)
     */
    *(unsigned int *)0x48180350 = 0;
    
    /*
     * (CM_DPLL) CM_AUDIOCLK_MCBSP_CLKSEL[1:0] CLKSEL = 0x0 - SEL1 : Select McBSP audio clock to be SYSCLK20
     */
    *(unsigned int *)0x48180388 = 0x0;
    
    /*
     * (PLLSS) McBSP_UART_CLKSRC[2:0] McBSP_CLKS_SOURCE = 0x0 (Source is CM_AUDIOCLK_MCBSP)
     */
    *(unsigned int *)0x481C52D8 = 0x0;
    
    /*
     * Configure the Audio PLL
     * N = 6
     * M = 160
     * M2 = 126
     * 22.5792 * 1/(6+1) * 160 * (1/126) = 4.096 MHz
     */
    cmdAUDIOPLL(22,6,160,126);
    
    /*
     * (PLLSS) McBSP_UART_CLKSRC [2:0] = 0 - Source is CM_AUDIOCLK_MCBSP
     */
    *(unsigned int *)0x481C52D8 = 0;
    
    
    GEL_TextOut("\tPRCM for McBSP are in Progress, Please wait.....  \n","Output",1,1,1);         
    
    WR_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Slow Domain Peripheral*/    
    
    WR_MEM_32(CM_ALWON_MCBSP_CLKCTRL,    0x2); /*Enable McBSP Clock*/
    while(RD_MEM_32(CM_ALWON_MCBSP_CLKCTRL)!=0x2);

    while(RD_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x1100 !=0x1100);

    GEL_TextOut("\tPRCM for McBSP are Done Successfully.....  \n","Output",1,1,1);      
    
    /*
     * MCBSP settings
     */
    GEL_TextOut("\tStart McBSP configuration.....  \n","Output",1,1,1);      
    /*
     *  110h SPCR2_REG - McBSP Serial Port Control Register 2
     *  SPCR2[6] - GRST = 0;
     *  SPCR2[0] - XRST = 0;
     *  SPCR2[7] - FRST = 0;
     */
    *(unsigned int *)0x47000110 = 0x0;
     /*
      * 114h SPCR1_REG - McBSP Serial Port Control Register 1
      * SPCR1[0] - RRST = 0;
      */
    *(unsigned int *)0x47000114 = 0x0;
     /*
      * 128h SRGR2_REG - McBSP Sample Rate Generator Register 2
      * SRGR2[13] - CLKSM = 1;
      * SRGR2[14] - CLKSP = 0;
      * SRGR2[15] - GSYNC = 0;
      */
    *(unsigned int *)0x47000128 = 0x00002000;
     /*
      * 148h PCR_REG - McBSP Pin Control Register
      * PCR[13] - XIOEN = 0;
      * PCR[3] - FSXP = 0;
      * PCR[1] - CLKXP = 0;
      */
    *(unsigned int *)0x47000148 = 0x0;
     /* 148h PCR_REG - McBSP Pin Control Register
      * PCR[9] - CLKXM = 1 - CLKX is an output pin and is driven by the internal SRG.
      *    PCR[10] - FSRM = 0 - Frame synchronization generated internally by SRG. FSR is an output pin except when GSYNC=1 in SRGR.
      *    PCR[11] - FSXM = 1 - Frame synchronization is determined by the SRG frame-synchronization mode bit FSGM in SRGR2.
      */
    *(unsigned int *)0x47000148 = 0x00000A00;
     /*
      * 110h SPCR2_REG - McBSP Serial Port Control Register 2
      * SPCR2[6] - GRST = 1
      */
    *(unsigned int *)0x47000110 = 0x00000040;
     /*
      * 114h SPCR1_REG - McBSP Serial Port Control Register 1
      * SPCR1[0] - RRST = 1
      */
    *(unsigned int *)0x47000114 = 0x1;
     /*
      * 110h SPCR2_REG - McBSP Serial Port Control Register 2
      * SPCR2[0] - XRST = 1
      */
    *(unsigned int *)0x47000110 = 0x00000041;
     /*
      * 110h SPCR2_REG - McBSP Serial Port Control Register 2
      * SPCR2[7] - FRST = 1
      */
    *(unsigned int *)0x47000110 = 0x000000C1;

I have attached the gel file

5153.DM8148_EVM.gel

Thanks,

HR

HR,

What is the AUDIO ADPLLJ CLKOUT value at this line:

McBSPClkEnable()
{
    UWORD32 m2nval,mn2val,read_clkctrl;
    UWORD32 clkin = 22.579, ref_clk, clkout_dco = 0, clk_out;
    UWORD32 N = 6, M = 160, M2 = 126;
 
    /*
     * Calculate the clock out
     */
    ref_clk     = clkin/(N+1);
    clkout_dco  = ref_clk*M;
    clk_out     = clkout_dco/M2;
    GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,clk_out);

I suspect there might be an issue with this int vs float values. clkin is defined as UWORD32 (unsigned int) at assigned with float value (22.579).

ref_clk is also defined as UWORD32 (unsigned int), while the value it gets is float (22.579/(6+1)). Same issue (int vs float) with clkout_dco and clk_out values.

DPLLJ also has an 18b fractional multiplier which is useful for configuring very specific frequencies as desired (for example, audio and video). See DM814x TRM, 2.6.1 DPLLLJ Fractional M-divider Programming, 2.6.4 DPLLLJ Frequency Factors, Table 2-155. AUDIOPLL_FRACDIV Register Field Descriptions.

BR
Pavel

Hi Pavel,

I'm getting 3, but shouldn't the below configuration work?

    /*
     * Configure the Audio PLL
     * N = 6
     * M = 160
     * M2 = 126
     * 22.5792 * 1/(6+1) * 160 * (1/126) = 4.096 MHz
     */
    cmdAUDIOPLL(22,6,160,126);

Do you see any issue with this configuration? Why don't we get something on the clkout0 pin?

Thanks,

HR

HR,

HRi said:

I'm getting 3, but shouldn't the below configuration work?

HRi said:

Why don't we get something on the clkout0 pin?

Hi Pavel,

We made a mistake with the clockout0 reading and we are getting 32.78 KHz atAE17 but we are getting the same clock (32.78 KHz) using cmdAUDIOPLL(22,6,160,126); or cmdAUDIOPLL(22,1,160,100);, the second one is just to see if we get a clock change, so possibly we have a routing clock mistake but where could it be? any chance you can check the gel setting on your board to see what you are getting?

Many Thanks,

HR

HRi,

It seems that on clkout0 we are routing audio pll clk1, and not audio pll clk3. The output clock from the Audio pll is audio pll clk3, the one that then is supplying the McBSP. While audio pll clk1 is the output clock from the RTCDIVIDER, which then supplies other modules like WDT0, GPIO, MMC, etc. (not McBSP). 

The path for audio pll clk1 is: DEVOSC(20MHz) -> RTCDIVIDER (divide 20MHz to 32.768KHz) -> audio pll clk1 (32.768 KHz) -> clkout0/1. See DM814x TRM, Figure 2-12. Audio Clock Structure. I am not really sure while this audio pll clk1 is named like this, it has nothing in common with the Audio PLL and audio modules (McBSP, McASP).

Also this is what we have in the DM814x_PG2.x.gel file, available at ti-ezsdk_dm814x-evm_5_05_02_00/board-support/host-tools/DM814x_gel.zip

//Clockout_Enable
    // CLKOUT2DIV THis  field controls the external clock divison factor
    //          0x0:      SYS_CLKOLUT2/1  
    //          0x1:      SYS_CLKOUT2/2  
    //          0x2:      SYS_CLKOUT2/4  
    //          0x3:      SYS_CLKOUT2/8  
    //          0x4:      SYS_CLKOUT2/16  
    
    // CLKOUT2SOURCE     This field selects the external output clock source
    //          0x0:      Source clock is MAIN_PLL_CLK5  
    //          0x1:      Source clock is DDR_PLL_CLK1  
    //          0x2:      Source clock is VIDEO_PLL_CLK1  
    //          0x3:      Source clock is AUDIO_PLL_CLK1  
 
    #define CLKOUT2EN    1
    #define CLKOUT2DIV  0
    #define CLKOUT2SRC  0

Sorry about this confusion, but clkout0/1 can not help us to check the Audio PLL output clock.

What is the clock frequency on the McBSP clk pin (MCB_CLKX) when using the below settings?

cmdAUDIOPLL(22,6,160,126)

cmdAUDIOPLL(22,1,160,100)

cmdAUDIOPLL(20,19,800,4);

Regards,
Pavel

Hi Pavel,

For - cmdAUDIOPLL(22,6,160,126) and  cmdAUDIOPLL(22,1,160,100) The McBSP clk is 50MHz, will check cmdAUDIOPLL(20,19,800,4); any idea where the 50MHz comes from?

Thanks,

HR

HR,

HRi said:

any idea where the 50MHz comes from?

I suspect that when you set the output clock (CLKOUT) of the Audio PLL to be 3MHz, while the minimum allowed value is 10MHz (see DM814x datasheet, section 7.4.6.3), the Audio PLL is actually providing 100MHz as an output clock. Then this clock goes through the McBSP SRG divider (SRGR1_REG[7:0] CLKGDV), where the dafault value is 0x1, which means that the 100MHz clock is divided by 2, before output on the MBC_CLKX pin, thus the 50MHz value.

CLKG has a frequency equal to 1/(CLKGDV + 1) of sample rate generator input clock.

Can you try to set 10MHz to the Audio PLL, will you receive 5MHz at the MCB_CLKX pin?

Regards,
Pavel

Hi Pavel,

We already tried - cmdAUDIOPLL(22,1,160,100), in the DM814x datasheet, section 7.4.6.3,  the frequences are related to OPP100, is there different freq. for different OPP? how do we set the OPP?

Thanks,

HR

HR,

HRi said:

We already tried - cmdAUDIOPLL(22,1,160,100)

With these values (CLKIN=22, N=1, M=160, M2=100), you are in the HS1 mode:

cmdAUDIOPLL(int CLKIN,int N, int M, int M2)
{
        DCOCLK_COMP(CLKIN,N,M);
        if(HSMODE == 2){  
            PLL_Clocks_Config(AUDIO_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2);
             GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
        }
        else if (HSMODE == 1){
            PLL_Clocks_Config(AUDIO_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1);
             GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
        }
        else {
                  GEL_TextOut("\t AUDIO PLL NOT Configured.Wrong DCOCLK Output\n");
        }

}

And this is not correct for Audio PLL:

/*************************************************************************************************************
                                   ADPLLJ CLKCNTRL REGISTER CONFIGURATIONS
                                   
***************************************************************************************************************/      
    // ADPLLJ_CLKCRTL_Register Value Configurations
    //add ntrim values for test device  --- Rajesh/Hemanth(bits 28:24)
    #define ADPLLJ_CLKCRTL_HS2       0x00000801 //HS2 Mode,TINTZ =1  --used by all PLL's except HDMI
    #define ADPLLJ_CLKCRTL_HS1       0x00001001 //HS1 Mode,TINTZ =1  --used only for HDMI
    #define ADPLLJ_CLKCRTL_CLKDCO    0x200a0000 // Enable CLKDCOEN,CLKLDOEN,CLKDCOPWDNZ -- used for HDMI,USB

HS1 mode is only for HDMI PLL, while for other PLLs (like Audio PLL), you should be in HS2 mode. So you need to choose other values for N and M parameters.

Also with these parameters (cmdAUDIOPLL(22,1,160,100)) your ref_clk is 11MHz, while the max allowed value is 2.5MHz, see DM814x datasheet, Table 7-22. Top-Level PLL Frequency Ranges (ALL OPPs)

HRi said:

the frequences are related to OPP100, is there different freq. for different OPP? how do we set the OPP?

See DM814x datasheet, Table 7-4. Device Operating Points (OPPs). You keep your ARM to the default 600MHz, right? Thus you are on OPP100. For switching to other OPP (OPP120, OPP166), you should increase the ARM (and eventually DSP, HDVICP, CORE) frequency and also increase the voltage from 1.1V to 1.2V/1.35V.

Best regards,
Pavel

Hi Pavel,

We tried cmdAUDIOPLL(CLKIN,19,600,100) which uses HS2 and the ref_clk is less than 2.5MHz and higher than 0.5MHz but still we get 50MHz on the McBSP clk,

Thanks,

HR

HR,

HRi said:

We tried cmdAUDIOPLL(CLKIN,19,600,100)

With these settings, you have clkout at 6.6MHz (or 6MHz), right?

And this is out of the Audio PLL clkout range, which is from 10MHz to 200MHz, see DM814x datasheet, Table 7-24. PLL CLKOUT Frequency Ranges.

Can you decrease M2 parameter (from 100 to lower value) to match with the requirements from Table 7-24. Do you have any difference on the McBSP clk pin?

Regards,
Pavel

Hi Pavel,

We changed the numbers to cmdAUDIOPLL(CLKIN,19,600,40) which should be ~17MHz but we still get the 50MHz on the McBSP clk,

Thanks,

HR

HR,

HRi said:

we still get the 50MHz on the McBSP clk

What is the value in SRGR1_REG[7:0] CLKGDV bitfield, is it 0x1 (reset value)? If you set the value of 0x9 in CLKGDV, will you get different frequency on McBSP clk pin?

Can you also try what will you have on McBSP clk pin, with the below configurations:

SCLKME = 0, CLKSM = 0 (CLKS pin)

SCLKME = 1, CLKSM = 0 (CLKR pin)

SCLKME = 1, CLKSM = 1 (CLKX pin)

BR
Pavel

Hi Pavel,

We solved the issue by setting SCLKME = 0 and CLKSM = 0 ,

Thank you for the great support !!!!

HR