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TVP70025 assistance request

Other Parts Discussed in Thread: TFP410, TVP7002

Application:

This is a PC-graphics only application and we only need to support the 15 formats listed at the top of the spread sheet.

We are using an external 27 MHz clock.

 

Q1. Is there a tolerance for the lines per frame and clocks per line?

 

Q2. Is the write-up, section 3 correct?

 

Q3. Since this is a PC-graphics only application which I2C sub-address registers can be ignored?

  • See attachments for additinal customer inputs ('section 3' portion of inquiry, below, refers to the 'DS2200 ... Word attachment).

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    We are  half way thru layout (we could still fix stuff) and I’d like to go over the TVP70025 with an applications engineer.

    References:  schematic, a write up (see section 3) and a register spread sheet.

    Application:

    This is a PC-graphics only application and we only need to support the 15 formats listed at the top of the spread sheet.

    We are using an external 27 MHz clock.

     

    Q1. Is there a tolerance for the lines per frame and clocks per line?

     

    Q2. Is the write-up, section 3 correct?

     

    Q3. Since this is a PC-graphics only application which I2C sub-address registers can be ignored?

    ***************************************************

    Thanks,

    Phil

  • Adding missing attachments ...

    Phil

     

     

  • Last attachment (can't seem to add multiple files to single post).

    Phil

     

    TVP70025 setup info.xlsx
  • Removed 2 attachments per customer request.

    Phil

  • Q1. Is there a tolerance for the lines per frame and clocks per line?

     A: To be safe, +/- 1 tolerance should be used for lines per frame and clocks per line statut readback.  An external 27MHz refernced clock is recommended for best results.

     A:  When the video or graphics input is disconnected the internal counters will not update and could retain old data. To ensure current status, toggle the CP_RESET bit in REG22h prior to reading the status registers.  A delay of at least 1 frame is required prior to reading lines per frame.

    Q2. Is the write-up, section 3 correct?

    A:  The TVP700x parts do not have a PLL lock status.  The status registers can be used to determine signal input status.

    A:  The input sync polarities change for the various graphics formats.  This needs to be taken into acccunt when reading the Sync Detect Status REG 14h.

    A:  SOGD (SOG detect) does not guarantee presence of sync-on-green.  It is actually 'any' signal present at the SOG input.

    A:  To prevent false sync detection, the input syncs should not be allowed to float when the input is disconnected.

    A:  There are limitations with the TVP7002x DE generaration that can lead to alignment issues for some graphics formats.  The TFP410 internal DE generation can be used to avoid this.

    Q3. Since this is a PC-graphics only application which I2C sub-address registers can be ignored?

    A: The same gain, offset, clamp, and ALC settings can be used for all graphics formats. 

    A: If the TFP410 internal DE generation is used, there is no need to program the AVID and VBLK start/stop settings in the TVP7002.

    A:  The color space converter is not needed for RGB in/out.  Default register settings can be used.

    A:  The H-PLL and sync polarities and widths must change for various graphics formats.  The sync settings must be correct for proper DVI transmission and mode detection in the monitor.

  • Thank you, Larry.

    I am closing out a crosspost in the etc / dataconvertersection, also.

    Phil

  • Crosspost answered in Specialty Forum section (see TVP72005 posts in that section).

    Inquiry closed.

    Phil