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How to enable mcasp0 High speed transmit clock by AHCLKX pin on AM3352 ?

jiabo yu
Intellectual 370 points
Other Parts Discussed in Thread: AM3352

Hi:

all.

I'm debugging audio codec of SGTL5000 now,the id of the audio codec  cann't be recognize;

and checking the master clock pin of AHCLKX ,the master clock isn't appered.

I'am using SDK-06.00.00.00,platform is am3352.

how to enable mcasp0 High speed transmit clock by  AHCLKX ?

the codec pin and am3352 pin is layout as follow:

SGTL5000                                AM3352

CTRL_DATA                             I2C0_SCL [mode0]

CTRL_CLK                               I2C0_SDA [mode0]

I2S_DOUT                               MCASP0_AXR0[mode0]

I2S_DIN                                    MCASP0_AXR1[mode0]

I2S_LRCLK                               MCASP0_FSX[mode0]

I2S_SCLK                                 MCASP0_ACLKX[mode0]

SYS_MCLK                               MCASP0_AHCLKX[mode0]

the following is my testing code in u-boot:

1，clock.c：
 
 /* McASP0 */  
writel(PRCM_MOD_EN, &cmper->mcasp0clkctrl);  while (readl(&cmper->mcasp0clkctrl) != PRCM_MOD_EN)；
 
2,mux.c:
static struct module_pin_mux mcsap0_pin_mux[] = { 
 {OFFSET(mcasp0_aclkx), (MODE(0) | PULLUDEN)}, /* mcasp0_aclkx */ 
 {OFFSET(mcasp0_fsx), (MODE(0) | PULLUDEN | PULLUP_EN)},   /* mcasp0_fsx */  
{OFFSET(mcasp0_axr0), (MODE(0) | PULLUDEN)}, /* mcasp0_axr0 */  
{OFFSET(mcasp0_axr1), (MODE(0) | PULLUDEN)},   /* mcasp0_axr1 */  
{OFFSET(mcasp0_ahclkx), (MODE(0) | PULLUDEN | PULLUP_EN)},   /* mcasp0_ahclkx */   {-1},
 };
 
configure_module_pin_mux(mcsap0_pin_mux);
 
could you give some ideal ?
Regards,
 
jiabo;

 

  • 0
    TI__Guru**** 393215 points
    Hi Jiabo,
     
    If this is really what you have connected:
     
    SGTL5000                                AM3352
    CTRL_DATA                             I2C0_SCL [mode0]
    CTRL_CLK                               I2C0_SDA [mode0]
     
    Then your I2C connection will not function at all. Clock and Data lines are crossed over.