DM3730 - jitter on the DSS_PCLK signal

sebastien72887

Prodigy 100 points

Other Parts Discussed in Thread: THS8200, DM3730

Hi,

We use DM3730 to DAC (THS8200) for VGA output.

We get defects on the screen, due to jitter on the DM3730 pixel clock DSS_PCLK.

We use the "display controler" driver on DM3730.

How to reduce this jitter ? What are PLL registers ?

Thank in advance,

seb.

over 12 years ago

0 Cvetolin Shulev-XID over 12 years ago

TI__Guru 65405 points

Hi Sebastien,

I recommend you to use the maximum priority for the task which makes sending the data to the DAC to reduce the jitter. If the system is under heavy load decrease the priority of the other tasks.

You can find information about PLL registers in the Technical reference manual - section 3.7.1.4 MPU_CM registers at he link below:

http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf

Tsvetolin Shulev

0 sebastien72887 over 12 years ago in reply to Cvetolin Shulev-XID

Prodigy 100 points

Hi,

"I recommend you to use the maximum priority for the task which makes sending the data to the DAC to reduce the jitter."

Why ??? the pixel clock does not come directly from the pll ?

How to define priority ?

We have jitter = 10ns at 20µs with pixel clock 64MHz (on beagleboard and custom board).

We have no jitter on our old custum board with Davinci DM6443.

Please, it's very urgently

seb

0 sebastien72887 over 12 years ago in reply to sebastien72887

Prodigy 100 points

please ?

thank in advance, seb.

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DM3730 - jitter on the DSS_PCLK signal