I am trying to set the PLL to a proper, specified clock frequency. I have a F28335 with an external 32 MHz crystal. I'm hoping to use a ratio of 9/2 to get 144 MHz. However, the program is defaulting to 10/2 resulting in an above-maximum clock rate of 160 MHz. I'm confirming this speed by checking the frequency of a PWM with period 1500. I'm getting an output period of 53.2 kHz (160 MHz / 2 / 1500) instead of 44 kHz (144 MHz / 2 / 1500). Even if I radically change the PLL constants to much lower values, the PWM frequency remains rock solid at 53.2 kHz.
I have observed the PLLCR [DIV] value still being 0xA and PLLSTS being 0x2 when pausing the program for additional confirmation.
Also, I have tried doing a clean build after saving the SYS/BIOS CFG file.
My settings are shown in this figure:
The relevant part of the CFG script is:
Boot.configurePll = true;
Boot.bootFromFlash = true;
Boot.pllOSCCLK = 32;
BIOS.cpuFreq.lo = 144000000;
Boot.pllcrDIV = 9;
According to SYS/BIOS for the C28x wiki page, the F28335 should be configurable this way. My steps match the wiki and this other thread. What am I missing?
CCS: 5.4.0.00091
SYS/BIOS: 6.35.1.29