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Mipi DSI Interleaving mode question

wu william
Intellectual 460 points
Other Parts Discussed in Thread: SYSCONFIG

Hi all


 

We met some problem about DSI transfer command.
We want to send the other command for register , When we use Video mode to send pixel data and sync event .
Refer OMAP TRM document "10.3.4.4.3.5 Interleaving Mode"
I have added patch 

[PATCH] OMAPDSS: DSI: Support command mode interleaving during video mode blanking periods


and I use dsi_vc_dcs_write_nosync  function to send command that I wanted.
but haven't seem any High speed package on LA.
And Display will crush.(but sync packet still alive)
shall we need to setting any register here??
thank you..

DSI_VC_CTRL(0)                      20800f90
DSI_VC_CTRL(0)                      20808fb1

this bit TX_FIFO_NOT_EMPTY always not clean.

DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1c

seems like Data stuck on TX FIFO
 
 
 
 
============= Send data before ==============
 
DSI_REVISION                        00000030
DSI_SYSCONFIG                       00000011
DSI_SYSSTATUS                       00000001
DSI_IRQSTATUS                       000000a0
DSI_IRQENABLE                       0015c000
DSI_CTRL                            00eaea99
DSI_COMPLEXIO_CFG1                  6a000021
DSI_COMPLEXIO_IRQ_STATUS            00000000
DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
DSI_CLK_CTRL                        a0346009
DSI_TIMING1                         7fff7fff
DSI_TIMING2                         ffff7fff
DSI_VM_TIMING1                      ff02c03e
DSI_VM_TIMING2                      04020c10
DSI_VM_TIMING3                      043401e0
DSI_CLK_TIMING                      00001712
DSI_TX_FIFO_VC_SIZE                 13121110
DSI_RX_FIFO_VC_SIZE                 13121110
DSI_COMPLEXIO_CFG2                  00030000
DSI_RX_FIFO_VC_FULLNESS             00000000
DSI_VM_TIMING4                      00000000
DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
DSI_VM_TIMING5                      0082df3b
DSI_VM_TIMING6                      ffff31d1
DSI_VM_TIMING7                      0012000f
DSI_STOPCLK_TIMING                  00000080
DSI_VC_CTRL(0)                      20808f91
DSI_VC_TE(0)                        00000000
DSI_VC_LONG_PACKET_HEADER(0)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
DSI_VC_SHORT_PACKET_HEADER(0)       00000000
DSI_VC_IRQSTATUS(0)                 00000004
DSI_VC_IRQENABLE(0)                 000000db
DSI_VC_CTRL(1)                      20808f81
DSI_VC_TE(1)                        00000000
DSI_VC_LONG_PACKET_HEADER(1)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
DSI_VC_SHORT_PACKET_HEADER(1)       00000000
DSI_VC_IRQSTATUS(1)                 00000000
DSI_VC_IRQENABLE(1)                 000000db
DSI_VC_CTRL(2)                      20808d81
DSI_VC_TE(2)                        00000000
DSI_VC_LONG_PACKET_HEADER(2)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
DSI_VC_SHORT_PACKET_HEADER(2)       00000000
DSI_VC_IRQSTATUS(2)                 00000000
DSI_VC_IRQENABLE(2)                 000000db
DSI_VC_CTRL(3)                      20808d81
DSI_VC_TE(3)                        00000000
DSI_VC_LONG_PACKET_HEADER(3)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
DSI_VC_SHORT_PACKET_HEADER(3)       00000000
DSI_VC_IRQSTATUS(3)                 00000000
DSI_VC_IRQENABLE(3)                 000000db
DSI_DSIPHY_CFG0                     0f22101b
DSI_DSIPHY_CFG1                     42050d2f
DSI_DSIPHY_CFG2                     b800000c
DSI_DSIPHY_CFG5                     e3000000
DSI_PLL_CONTROL                     00000000
DSI_PLL_STATUS                      00000383
DSI_PLL_GO                          00000000
DSI_PLL_CONFIGURATION1              14a12c1f
DSI_PLL_CONFIGURATION2              00656008
 
 
=============Send data after ==============
 
 
 
DSI_REVISION                        00000030
DSI_SYSCONFIG                       00000011
DSI_SYSSTATUS                       00000001
DSI_IRQSTATUS                       000000a0
DSI_IRQENABLE                       0015c000
DSI_CTRL                            00eaea99
DSI_COMPLEXIO_CFG1                  6a000021
DSI_COMPLEXIO_IRQ_STATUS            00000000
DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
DSI_CLK_CTRL                        a0346009
DSI_TIMING1                         7fff7fff
DSI_TIMING2                         ffff7fff
DSI_VM_TIMING1                      ff02c03e
DSI_VM_TIMING2                      04020c10
DSI_VM_TIMING3                      043401e0
DSI_CLK_TIMING                      00001712
DSI_TX_FIFO_VC_SIZE                 13121110
DSI_RX_FIFO_VC_SIZE                 13121110
DSI_COMPLEXIO_CFG2                  00030000
DSI_RX_FIFO_VC_FULLNESS             00000000
DSI_VM_TIMING4                      00000000
DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1c
DSI_VM_TIMING5                      0082df3b
DSI_VM_TIMING6                      ffff31d1
DSI_VM_TIMING7                      0012000f
DSI_STOPCLK_TIMING                  00000080
DSI_VC_CTRL(0)                      20808fb1
DSI_VC_TE(0)                        00000000
DSI_VC_LONG_PACKET_HEADER(0)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
DSI_VC_SHORT_PACKET_HEADER(0)       00000000
DSI_VC_IRQSTATUS(0)                 00000004
DSI_VC_IRQENABLE(0)                 000000db
DSI_VC_CTRL(1)                      20808f81
DSI_VC_TE(1)                        00000000
DSI_VC_LONG_PACKET_HEADER(1)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
DSI_VC_SHORT_PACKET_HEADER(1)       00000000
DSI_VC_IRQSTATUS(1)                 00000000
DSI_VC_IRQENABLE(1)                 000000db
DSI_VC_CTRL(2)                      20808d81
DSI_VC_TE(2)                        00000000
DSI_VC_LONG_PACKET_HEADER(2)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
DSI_VC_SHORT_PACKET_HEADER(2)       00000000
DSI_VC_IRQSTATUS(2)                 00000000
DSI_VC_IRQENABLE(2)                 000000db
DSI_VC_CTRL(3)                      20808d81
DSI_VC_TE(3)                        00000000
DSI_VC_LONG_PACKET_HEADER(3)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
DSI_VC_SHORT_PACKET_HEADER(3)       00000000
DSI_VC_IRQSTATUS(3)                 00000000
DSI_VC_IRQENABLE(3)                 000000db
DSI_DSIPHY_CFG0                     0f22101b
DSI_DSIPHY_CFG1                     42050d2f
DSI_DSIPHY_CFG2                     b800000c
DSI_DSIPHY_CFG5                     e3000000
DSI_PLL_CONTROL                     00000000
DSI_PLL_STATUS                      00000383
DSI_PLL_GO                          00000000
DSI_PLL_CONFIGURATION1              14a12c1f
DSI_PLL_CONFIGURATION2              00656008
 
  • 0
    Intellectual 460 points

    We have modified 

    1. DSI_VM_TIMING6                      0xffff31d1 (BL_HS_INTERLEAVING to 0xffff)
    2. r = FLD_MOD(r, 0, 20, 20);     /* BLANKING_MODE */

    r = FLD_MOD(r, 1, 21, 21);     /* HFP_BLANKING */

    r = FLD_MOD(r, 1, 22, 22);     /* HBP_BLANKING */

    r = FLD_MOD(r, 1, 23, 23);     /* HSA_BLANKING */

    dsi_write_reg(dsidev, DSI_CTRL, r);

    shall we need to setting other register here??

    thank you.