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C667x sRIO BER testing with the embedded test patterns generation and detection

Daisuke Maeda
Guru 20205 points

Could you tell me the method of the BER (Bit Error Rate) testing?

SRIO_SERDES_CFGRX[0-3].TESTPATTERN can select the detected test patterns.
SRIO_SERDES_CFGTX[0-3].TESTPATTERN can select the generated test patterns.
SP[0-3]_ERR_RATE.Error Rate Counter can maintain a count of the number of transmission errors.

Can these bits be used for the BER testing? If they can, what procedure should the BER testing be performed in?

The required test patterns are unique to the two levels of link.

For Level I the test pattern is the CJPAT defined in Annex 48A of IEEE802.3ae.
Can the CJPAT defined in Annex 48A of IEEE802.3ae be tested? If that can, what procedure should the CJPAT testing be performed in?

For Level II the test pattern is the PRBS31 defined in ITU-T 0.150.
Does it detect the PRBS31 defined in ITU-T 0.150 that "100b" is set to the SRIO_SERDES_CFGRX[0-3].TESTPATTERN?
Does it generate the PRBS31 defined in ITU-T 0.150 that "100b" is set to the SRIO_SERDES_CFGTX[0-3].TESTPATTERN?

Can other test patterns selected in the TESTPATTERN bits be used for the BER testing?

Best regards,

Daisuke

 

  • 0
    TI__Genius 13235 points

    Hi Daisuke,

    I'll be looking into your questions. Feel free to post any additional information or questions in the meantime.

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Guru 20205 points

    Hi Clinton,

    Thank you for your reply.

    Our customer is using C6678 with IDT TSI578 and CPS-1848 as the SRIO switch device and wants to perform the BER testing on individual lanes between a C6678 and a switch.

    TSI578 and CPS-1848 have on individual lanes the PRBS test patterns generation and detection capability.

    Our customer is in a very great hurry! They want to perform the testing in a few days.
    I would be grateful if you could reply as soon as possible.

    Best regards,

    Daisuke

     

  • 0
    TI__Genius 13235 points

    Hi Daisuke,

    Please see Advisory 17 - Corruption of Control Characters in SRIO Line Loopback Mode Issue in the errata document for C6678 (http://www.ti.com/lit/pdf/sprz334). Given the content of this advisory, it will not be possible to use any test patterns that could send characters that could cause corruption (this includes PRBS).

    As the advisory suggests, it is possible to qualify your boards using Rapio-IO compliant data on the link instead.

    Thanks,
    Clinton

  • 0 in reply to Clinton Rodgers
    Guru 20205 points

    Hi Clinton,

    Thank you for your reply.

    I could understand that the line loopback mode is not available for the BER testing.

    Can the BER testing not perform without using the line loopback?

    The SRIO switches on the customer board have on individual lanes the PRBS test patterns generation and detection capability.
    I guess that the BER testing can perform between a transmitter and a receiver if the C6678 has the same capability.

    Best regards,

    Daisuke

     

  • 0 in reply to Clinton Rodgers
    Guru 20205 points

    Hi Clinton,

    SRIO_SERDES_CFGTX[0-3].TESTPATTERN can select the generated test patterns. Can these test patterns be used for the BER testing?

    If so C6678 have on individual transmitters the PRBS test patterns generation capability. And the SRIO switches on the customer board have on individual receivers the PRBS test patterns detection capability.

    Our customer performed the BER testing between the C6678's transmitters and the switch's receivers. It could be performed on lane 0, lane 1 and lane 2, but could not be performed on lane 3.

    Best regards,

    Daisuke

     

  • 0 in reply to Clinton Rodgers
    Guru 20205 points

    Hi Clinton,

    Please give me an answer as soon as possible.
    Your prompt reply would be appreciated.

    For the BER testing on the customer board, a switch's receiver detects the PRBS test patterns that a C6678's transmitter generates. It can be performed on lane 0, lane 1 and lane 2 with no error, but can detect no pattern on lane 3.
    Our customer wants to know why no pattern can be detected on lane 3.
    I guess the C6678 does not support the PRBS test patterns generation. Does the C6678 support the PRBS test patterns generation?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 23525 points

    There should be no difference for lane 3.  All lanes should work the same.  The advisory that Clinton pointed you to is for Line loopback only, so there shouldn't be any problem generating the PRBS on TX.  There is no PRBS checking on RX though.  Make sure you have RIO_PER_SET_CNTL[3:0]=0b1111.


    Regards,

    Travis

  • 0 in reply to tscheck
    Guru 20205 points

    Hi Travis,

    Thank you for your reply.

    Has it been confirmed by TI that the PRBS test patterns are generated and available for the BER testing?

    Best regards,

    Daisuke

     

  • 0 in reply to tscheck
    Guru 20205 points

    Hi Travis,

    Daisuke Maeda said:

    Has it been confirmed by TI that the PRBS test patterns are generated and available for the BER testing?

    Our customer wants to know whether it should not be used for the BER testing. If it is not confirmed and not guaranteed by TI, they will assume that it should not be used for the BER testing.

    Please give me an answer as soon as possible.
    Your prompt reply would be appreciated.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Intellectual 460 points
    Don't know if this helps: I could successfully run PRBS Tx test pattern on both, C6657 and C6678 EVM to an FPGA and there succesfully verify error free reception. This was done on lane 0&1 initially, but later on also on lane 2&3. Also, two different patterns were used: 7-bit PRBS and 31-bit PRBS. Sot DSP transmit is ok. My problem is to verify DSP reception, but that's another topic. Best regards Guenter
  • 0 in reply to Günter
    Guru 20205 points

    Hi Gunter,

    Thank you for your information. That is very helpful. However, the customer needs an comment from TI.

    Is there the special setting process for register configuration of the PRBS test pattern generation? The customer wants to know the correct process.

    Best regards,

    Daisuke

     

  • 0 in reply to Günter
    TI__Mastermind 23525 points

    I'm not aware of any TI testing of this feature.  Having said that, as Gunter, points out, it should work.

    Regards,

    Travis

     

  • 0 in reply to tscheck
    Guru 20205 points

    Hi Travis,

    Thank you for your reply.

    Best regards,

    Daisuke

     

  • 0 in reply to Günter
    Guru 20205 points

    Hi Gunter,

    Daisuke Maeda said:

    Is there the special setting process for register configuration of the PRBS test pattern generation? The customer wants to know the correct process.

    Can you show the source code that you used for the BER testing?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Intellectual 460 points
    Hi Daisuke, On the DSP side I have a slightly modified version of SRIO_LoopbackTestProject, modified for no loopback, 5Gbps and dual lane operation on lane 2&3. use a local copy of pdk_C6678_1_1_2_6/packages/ti/drv/srio/device/device_srio_loopback.c. Changes to device_srio_loopback.c: CSL_SRIO_SetLoopbackMode(); --> CSL_SRIO_SetNormalMode(); CSL_BootCfgSetSRIOSERDESConfigPLL (0x229); --> CSL_BootCfgSetSRIOSERDESConfigPLL ( 0x00000200 | /* VRANGE=1 */ 0x00000040 | /* MPY=20h=x8(sprugw1b,Table3-4)=x32=312.5*32=10GHz */ 0x00000001); /* ENPLL */ CSL_BootCfgSetSRIOSERDESTxConfig (, 0x00180795);--> CSL_BootCfgSetSRIOSERDESTxConfig (, 0x001A0795); CSL_BootCfgSetSRIOSERDESTxConfig (, 0x00180795);--> CSL_BootCfgSetSRIOSERDESTxConfig (, 0x000A0795); CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);--> CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 3); for(i = 0; i while (CSL_SRIO_IsPortOk (hSrio, 2) != TRUE); /* lanes 2&3 */ I start debugging, let the DSP run and then stop it. Usually it stops at polling the 'IsPortOK' flag (see above), because the remote side (FPGA) is loaded with a BER tester rather than an SRIO core. Now I display the CFGTX registers for lane 2 &3 (0x02620378, 0x02620380) and patch them from 0x001A0795 to 0x021A0795 and from 0x000A0795 to 0x020A0795 to generate the PBRS 31-bit test pattern. As soon as I have done this, the BER tester in the FPGA displays 5Gbps link rate and no bit errors. So in my configuration, lane 3 definitely supports PRBS-31 and also PRBS-7. Operation at 1.25Gbps (Rate 01-->11) works as well. best regards Guenter If you have trouble with lane 3, please check your settings. registers and simply patch to generate e.g. a 31-bit PRBS test pattern.
  • 0 in reply to Günter
    Intellectual 460 points
    Hi, My last posting contained some trailing text fragments, please ignore them & sorry for that. Guenter
  • 0 in reply to Günter
    Guru 20205 points

    Hi Gunter,

    Thank you for your great help.

    Have you tested another 2x port (lane 0&1) and 4x lane port in the same way?

    Why are MSYNC and TWPST1 in the CFGTX registers changed? Are the changes necessary for the any PRBS generation?

    I'm sorry. I cannot understand all of the changes because I am not well versed in the hardware.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Intellectual 460 points
    Hi Daisuke, Yes, originally I tested on lane 0&1 using the same settings except for CSL_SRIO_SetPLMPortPathControlMode () where I probably used mode 2 (2/1/1 lanes configuration). The change to lane 2&3 was done because I killed RIORXP0 somehow. Testing all 4 lanes wasn't done and isn't required in my project. MSYNC must be set for the 1st lane of each port, as somwhere stated in sprugw1b. For mode 4 it needs to be set in CFGTX0 only. TWPST was modified as a result of experimenting with different equalizer values, however, it doesn't change much and shouldn't play a role for you. If you have trouble with only one single lane, it might be worth checking for a hardware defect. If you have access to the pins, you can measure the DC voltage of each signal before and after the DC blocking capacitors (hope you have them). This way I discovered my defective lane. Best regards Guenter
  • 0 in reply to Günter
    Guru 20205 points

    Hi Gunter,

    Thank you for your reply.

    I guess that your configuration for 2x port should work when the link partner has only 4x port with 5Gbps lanes. I am going to suggest to our customer that they use your configuration first.

    Is the following correct as your changes to device_srio_loopback.c?

    ////////////////////////////////////////////////////////////////////////////////////////////////////

        /* Configure SRIO ports to operate in normal mode. */
        CSL_SRIO_SetNormalMode(hSrio, 0);
        CSL_SRIO_SetNormalMode(hSrio, 1);
        CSL_SRIO_SetNormalMode(hSrio, 2);
        CSL_SRIO_SetNormalMode(hSrio, 3);

        /* Assuming the link rate is 5Gbps; program the PLL accordingly. */
        CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

        /* Configure the SRIO SERDES Transmit Configuration. */
        CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
        CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00180795);
        CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x001A0795);
        CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x000A0795);

        /* Configure the path mode for the ports. */
        for(i = 0; i < 4; i++)
            CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 3);

        /* This code checks if the ports are operational or not. The functionality is not supported
         * on the simulator. */   
     for(i = 0; i < 4; i++)
            while (CSL_SRIO_IsPortOk (hSrio, 2) != TRUE);

    ////////////////////////////////////////////////////////////////////////////////////////////////////

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Intellectual 460 points
    Daisuke, two chenges to your code: 1) TxConfig #1 must have its MSYNC bit cleared. 2) The 'IsPortOK' check must be run on the index corresponding to the first lane only. In your case (Lane 0 + 1), SP0_ERR_STAT must be checked while in my case (2x config on lane 2+3) SP2_ERR_STAT must be checked. The TI example uses 1x confguration on all 4 lanes, resulting in 4 ports and thus, all 4 SPx_ERR_STAT must be checked. Best regards Guenter
  • 0 in reply to Günter
    Guru 20205 points

    Hi Gunter,

    Thank you for your time.

    Our customer wants to know a procedure for the BER testing using the PRBS test patterns confirmed by TI. I should confirm with TI whether your procedure is reliable.

    Are the following changes correct for your case (2x config on lanse 2+3)?

    ////////////////////////////////////////////////////////////////////////////////////////////////////

        /* Configure SRIO ports to operate in normal mode. */
        CSL_SRIO_SetNormalMode(hSrio, 0);
        CSL_SRIO_SetNormalMode(hSrio, 1);
        CSL_SRIO_SetNormalMode(hSrio, 2);
        CSL_SRIO_SetNormalMode(hSrio, 3);

        /* Assuming the link rate is 5Gbps; program the PLL accordingly. */
        CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

        /* Configure the SRIO SERDES Transmit Configuration. */
        CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x001A0795);
        CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x000A0795);

        /* Configure the path mode for the ports. */
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 0, 0);
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 1, 0);
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 2, 3);
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 3, 0);

        /* This code checks if the port 2 is operational or not. The functionality is not supported
         * on the simulator. */
        while (CSL_SRIO_IsPortOk (hSrio, 2) != TRUE);

    ////////////////////////////////////////////////////////////////////////////////////////////////////

    Are the following changes correct for our customer case (4x config)?

    ////////////////////////////////////////////////////////////////////////////////////////////////////

        /* Configure SRIO ports to operate in normal mode. */
        CSL_SRIO_SetNormalMode(hSrio, 0);
        CSL_SRIO_SetNormalMode(hSrio, 1);
        CSL_SRIO_SetNormalMode(hSrio, 2);
        CSL_SRIO_SetNormalMode(hSrio, 3);

        /* Assuming the link rate is 5Gbps; program the PLL accordingly. */
        CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

        /* Configure the SRIO SERDES Transmit Configuration. */
        CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
        CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00080795);

        /* Configure the path mode for the ports. */
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 0, 4);
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 1, 0);
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 2, 0);
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, 3, 0);

        /* This code checks if the port 0 is operational or not. The functionality is not supported
         * on the simulator. */
        while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE);

    ////////////////////////////////////////////////////////////////////////////////////////////////////

    Additionally, the TESTPATTERN field in the SERDES_CFGTXn_CNTL registers is set for the PRBS test patterns generation after the DSP running stops at polling the 'IsPortOK' flag.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Intellectual 460 points
    Daisuke, According to my small experience, the mode must be set up the same for all four ports. So please use /* Configure the path mode for the ports. */ CSL_SRIO_SetPLMPortPathControlMode (hSrio, 0, 3); CSL_SRIO_SetPLMPortPathControlMode (hSrio, 1, 3); CSL_SRIO_SetPLMPortPathControlMode (hSrio, 2, 3); CSL_SRIO_SetPLMPortPathControlMode (hSrio, 3, 3); for my case or /* Configure the path mode for the ports. */ CSL_SRIO_SetPLMPortPathControlMode (hSrio, 0, 4); CSL_SRIO_SetPLMPortPathControlMode (hSrio, 1, 4); CSL_SRIO_SetPLMPortPathControlMode (hSrio, 2, 4); CSL_SRIO_SetPLMPortPathControlMode (hSrio, 3, 4); for your case. Anyway, this probably hasn't an effect on PRBS operation. Best regards Guenter P.S.: If you have problems witgh lane 3, you may want to check this thread: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/196080.aspx This solved external loopback connection problem in my case.
  • 0 in reply to Günter
    Guru 20205 points

    Hi Gunter,

    Thank you for your reply. Sorry for taking your precious time.

    Our customer expects that the configuration for the PRBS test generation is incorrect, because the switches as the BER test equipments have never detected the test patterns on lane 3 and there is no error on other lanes.

    I am going to confirm with TI whether the following procedure is reliable.

    For your case (2x config on lanse 2+3):

    ////////////////////////////////////////////////////////////////////////////////////////////////////

        /* Configure SRIO ports to operate in normal mode. */
        CSL_SRIO_SetNormalMode(hSrio, 0);
        CSL_SRIO_SetNormalMode(hSrio, 1);
        CSL_SRIO_SetNormalMode(hSrio, 2);
        CSL_SRIO_SetNormalMode(hSrio, 3);

        /* Assuming the link rate is 5Gbps; program the PLL accordingly. */
        CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

        /* Configure the SRIO SERDES Transmit Configuration. */
        CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x001A0795);
        CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x000A0795);

        /* Configure the path mode for the ports. */
        for(i = 0; i < 4; i++)
            CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 3);

        /* This code checks if the port 2 is operational or not. The functionality is not supported
         * on the simulator. */
        while (CSL_SRIO_IsPortOk (hSrio, 2) != TRUE);

    ////////////////////////////////////////////////////////////////////////////////////////////////////

    For our customer's case (4x config):

    ////////////////////////////////////////////////////////////////////////////////////////////////////

        /* Configure SRIO ports to operate in normal mode. */
        CSL_SRIO_SetNormalMode(hSrio, 0);
        CSL_SRIO_SetNormalMode(hSrio, 1);
        CSL_SRIO_SetNormalMode(hSrio, 2);
        CSL_SRIO_SetNormalMode(hSrio, 3);

        /* Assuming the link rate is 5Gbps; program the PLL accordingly. */
        CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

        /* Configure the SRIO SERDES Transmit Configuration. */
        CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
        CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00080795);

        /* Configure the path mode for the ports. */
        for(i = 0; i < 4; i++)
            CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 4);

        /* This code checks if the port 0 is operational or not. The functionality is not supported
         * on the simulator. */
        while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE);

    ////////////////////////////////////////////////////////////////////////////////////////////////////

    Additionally, the TESTPATTERN field in the SERDES_CFGTXn_CNTL registers is set for the PRBS test patterns generation after the DSP running stops at polling the 'IsPortOK' flag.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Genius 13235 points

    Hi Daisuke,

    I'm glad that the customer has been able to get the PRBS tests working on lanes 0, 1 and 2. If they are using the same procedure on lane 3, there may be an issue with that connection.

    Do they have the equipment to probe that lane as Gunter suggested?  They could look at the eye diagram or if the set the Alternating 0/1 pattern, they could look for this clock signal being generated.

    Could they also provide the SRIO SERDES configuration register dump after the tests are running (i.e. the SRIO SERDES registers being set by their code)?

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Guru 20205 points

    Hi Clinton,

    Thank you for your reply.

    Unfortunately the customer does not have the equipment to probe the eye diagram or the clock signal. There are only the SRIO switches that have the PRBS test patterns generation and detection capability.

    The SRIO SERDES configuration registers have never been checked after the tests are running. I am going to ask them whether they can provide it.

    They want to consume time and labor only for the tests with correct configuration and procedure, hence have not tried Gunter's test procedure. Can you predicate that Gunter's procedure is reliable?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Genius 13235 points

    Hi Daisuke,

    There may be an issue with their connection of lane 3. They will most likely need to do some hardware debug, as Gunter did to determine where the issue is. I plan to test out the SRIO PRBS generation (TX) functionality on all the SRIO lanes of the C6678 EVM. I will post my results here sometime next week.

    For SRIO PRBS pattern generation, there should be no issues, as they've found on lanes 0-2. For SRIO PRBS verification (RX), there is not a way to perform BER testing. The RX TESTFAIL bit in the SRIO_SERDES_STS register only tells you if the test is currently passing or failing. There is no associated error counter.

    Let us know if you have any other questions or concerns.

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Guru 20205 points

    Hi Clinton,

    Thank you for your great help.

    I requested to the customer that they try the BER testing with Gunter's test procedure. I am waiting for their reply.

    Best regards,

    Daisuke

     

  • 0 in reply to Günter
    Intellectual 605 points
    Hi Gunter,

    I am trying to test the SRIO lanes between C6670 and FPGA. I came across this post and thought that I can use the test pattern to perform the test. I am trying to figure out the configuration for this test, like do I need to build the packet, LSU etc. It would be really helpful if you can provide the high level procedure for this test.

    Regards,
    Hari
  • 0 in reply to Hari..
    TI__Mastermind 23525 points

    PRBS testing on Keystone devices won't work.  Here's why.  Yes you can generate a PRBS test pattern by setting the PRBS override button in the per_set_cntl register, then programming the TX SerDes config registers as discussed above.  However, there is really no way to test the RX path.  The error indication bit that the RX SerDes has, is not a sticky bit, meaning that even if there is a transmission error, the bit will not hold state once it starts to receive a good pattern again.  There is no error counting either, so you can really never detect a RX error from PRBS.  There is also an errata that prohibits PRBS signals from being looped backed (RX-to-TX), so you can't hook up an external generator send a PRBS to the SoC, then loop back to an external PRBS receiver.  In short, it won't work and there really is no workaround.

    Regards,

    Travis

  • 0 in reply to tscheck
    Intellectual 605 points

    Thank you Travis. Can you help me in testing the SRIO in line loopback mode. I have posted a question in separate thread. Below is the link to the thread.

    https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/441707

    Thanks

    Hari