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PRU-ICSS as I2C servicer

Chip Burns
Prodigy 10 points

I've been tasked with implementing the PRU-ICSS as the I2C servicer for the 3 I2C channels on the core processor (CortexA8).  Have been studying the AM335x PRU-ICSS Reference Guide and am a little overwhelmed.

First, does this approach make sense?

Second, can I route the CortexA8 I2C status and/or interrupts and/or data to the PRU and vice versa?  If so, how?  I'm having difficulty understanding how the PRU 'sees' the Cortex.  Is it via the L3/L4 interface or the EGPIO?

 

Thx

Chip Burns