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need help for the power-on reset about C6678

Feng
Expert 2985 points

Hi all,

I had work out my own C6678 board. But when I tried to power on the chip then boot it, I met some questions below.

I had write a FPGA code to complete the power-on sequence. The sequence is :

CVDD-->CVDD_Fixed--->1.8V--->Coreclk, DDRclk, PASSclk--->1.5V--->0.75V--->de-assert RESET and drive the BOOTMODE[12:0]=0b0101000000110--->de-assert POR--->de-assert RESETFULL.

After the sequence is done,

1. I detect that the C6678's SYSCLKOUT pin outputs 16.6MHz(Coreclk=100MHz and SYSCLKOUT=1/6 Coreclk) and the RESETSTAT pin outputs hign level.

2. When I use the CCSv5 to debug a project, it shows me that "The Device is held in RESET". I am really confued about this problem. Does it cause by the PLL bypass problem? Or other problems? I had detect the RESETSTAT pin outputs the high level already!

It means that the C6678's Main PLL is still in bypass mode. But I think my chip is PG2.0. And as I know, the PG2.0 does not have the PLL problem like that.

So I want you to help me to confirm that:

1. If I use the PG2.0 chip, the PLL will be locked immediately and the chip will goes on when I just have the right power on sequence and set the BOOTMODE to SPI BOOT mode(or NO BOOT mode). Is it right?

2. If I want to fix the PLL, could I use the GEL file to configure the PLL when I set the chip to SPI BOOT mode? And how to write the GEL file? Are there any examples?

Appreciate for any helps!

Yours,

Feng

  • 0
    TI__Mastermind 42545 points

    Hi Feng,

    You appear to have the power sequencing correct. Based on you message, I'm assuming that you are using the SPI boot mode. SPI bootmode bypasses the PLL and operates the core at the reference clock frequency so 16.6MHz is the expected output frequency at the SYSCLKOUT pin. You can program the PLL using the a gel after you have connected with CCS. An example of that gel should be available as part of the MCSDK software release or with the software delivered with the EVM.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 2985 points

    Thanks Bill!

    Do you mean that the SPI BOOT mode will bypass the C6678's Main PLL whether the chip is PG1.0 or PG2.0?

    .

    If it is right, then I have another question :

    As I know if I set the C6678 to SPI BOOT mode, after the power on sequence, the Main PLL is in bypass mode. And then the RBL will copy the secondary bootloader from the SPI FLASH then to configure the PLL to make it work.

    But when the Main PLL is in bypass mode (just the power on sequence is done) and the C6678's core0 does not work, how does the RBL copy the secondary bootloader and excute it? Does this procedure need not the C6678 core to work in a normal frequence such as 1GHz or 1.25GHz?

    Does this mean that before boot procedure is done in SPI BOOT mode, the boot procedure will go on although the C6678's core does not work?

    Yours,

    Feng

  • 0 in reply to Feng
    TI__Mastermind 42545 points

    Hi Feng,

    You stated that when the main PLL is in bypass that the C6678 core0 does not work. That isn't true. The C6678 can operate with the PLL in bypass, however, a minimum core frequency is needed to support all of the peripherals of the device. Since the SPI memory can be accessed slowly, the C6678 can operate at the reference frequency while reading the secondary boot code. Once the code is read from the SPI memory, it can be used to initialize the PLL to the higher system clock frequency. This higher operating frequency will allow the DDR3 and other high speed peripherals to operate at their intended speeds. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 2985 points

    Very useful information!!

    And the last question:

    When the Main PLL was in bypass mode and the SYSCLK pin outputed 16.67MHz, I got a message that "Device is held in reset" from the CCS when I tried to debug the C6678 and the debug procedure was terminated. Is it just because the C6678 is in bypass mode?

    Yours,

    Feng

  • 0 in reply to Feng
    TI__Mastermind 42545 points

    Hi Feng,

    You should be able to connect with CCS when the device is in bypass mode. Since your RESETSTAT is high the device should be out of reset and accessible. You may have a configuration issue that is preventing connection.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 2985 points

    Hi Bill,

    .

    You mean the configuration issues in CCS IDE ? What kind of configuration issues?

    I just created a new project and wrote a simple code to print "Hello world!" in the console.

    No GEL files. NO CMD files. Just want to test a connection to the C6678's core0.

    Had a "target configuraion" cxml file to configure the XDS5260v2 cable. And the "test connection" option showed me that "The JTAG DR integrity had be scanned successfully"( I forgot the exact message but somethings like this).

    Could you show me more detail information about the "device is held in reset question"?

    .

    Sorrry for my stupid questiones. I am just a newcomer to CCS and DSP coding.

    Yours,

    Feng

  • 0 in reply to Feng
    TI__Mastermind 42545 points

    Hi Feng,

    I am not a CCS expert. I would suggest you open an new thread with this question so that I can highlight it to the CCS experts.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 2985 points

    Hi Bill,

    Thanks!! You had help me to make the C6678 boot sequence clear in my mind.

    I'll take your advice. The new thread link is http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/287044.aspx.

    Yours,

    Feng