Hi all,
I had work out my own C6678 board. And I set the C6678 to SPI BOOT mode. Before I wrote a secondary bootloader to initialize the C6678's Main PLL, the Main PLL is in bypass mode. And I detected the SYSCLK pin outputed 16.6MHz (in my board the COREclk is 100MHz) and the RESETSTAT pin outputed high level.
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Then I wrote a simple code to show "Hello world!" in the console.
NO GEL files. NO CMD files. Just wanted to test connection to the C6678 core0.
Had a "target configuraion" cxml file to configure the XDS5260v2 cable. And the "test connection" option showed me that "The JTAG DR integrity had be scanned successfully"( I forgot the exact message but somethings like this).
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But the CCS show me that "Device is held in reset" when I tried to debug this simple code. I was confused because the C6678's RESETSTAT pin outputed high level already.
Does I have any configuration issues in the CCS IDE?
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Appreciate for any helps!
Yours,
Feng