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Memory write cycles in TMS320C674x

Selvi P T
Prodigy 70 points

Hi All,

I am measuring the cycles required for reading a byte and writing a byte from/to DDR3 memory with cache enabled.

I observed that the cycle for reading a single byte is <1 cycle and writing a single byte is 6 cycles.Will it take 6 cycles for a single byte write?

Kindly help.

Thanks,

Selvi

  • 0
    TI__Expert 4760 points

    Hi Selvi,

    Which device are you using?

    For read If the default burst burst size is 8, the DDR2/mDDR memory controller returns 8 pieces of data for every read command it should be more than

    All writes have a burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed

    If the transfer request is for less than 8 words, depending on the scheduling result and the pending

    Commands, the DDR2/mDDR memory controller can

    • Mask out the additional data using DDR_DQM outputs

    • Terminate the write burst and start a new write burst

    Regards

    Antony

  • 0 in reply to Antony Samsunil
    Prodigy 70 points

    Dear Antony,

    Thanks for your inputs.

    We use Jacinto 5 device.

    Could you please provide more details on burst read and write?

    We are trying to copy 4k data from buffer A to buffer B. We measure cycles using TSCL register. We obtain around 26,500 cycles for this copy.

    Is this acceptable?

    Thanks,

    Selvi