AM335x internal system bus

Thanks for asking.

Please check our TRM. Each chapter has a block diagram with the internal connections...

http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=spruh73i

Hi and thanks for your answer.

I'm still having a hard time to figure out the overall structure of the SoC and what busses are used for internal communication ? how are the peripherals in the SoC communicating. Is the bus 128bit wide and on what speed ? 

I just need some idea of how it runs inside because I'm looking into how to exploits different peripherals for my custom board. 

Regards

Einar

It is unclear why information about the internal bus structure is important for how you use peripherals on your own target hardware.  In internal bus structure doesn't get exported to the outside world.

Perhaps you could provide some detail on why this is important to you.

However, they internal bus structure is Intellectual Property of TI and not necessarily something that is shared.

well for various reasons.  We are in the design phase of a new custom board and we are looking into how we can have high speed communication to a expansion board, second ETH and more and I am just looking into if any means of data traffic is better or worse for the processor. 

Is it feasible to have the second ETH on PCIe, while using DMA transfer for the expansion board and so on. But I know eventually everything has to go through the internal bus of the chip so I'm just wondering if it is a single bus communicating different peripherals inside the SoC or are there more. 

Hope this explanation makes sense. 

Einar Bjorgvinsson said:

Is it feasible to have the second ETH on PCIe, while using DMA transfer for the expansion board and so on.

I'm not sure I quite follow your question regarding the second ethernet on PCIe.  Please clarify this.

Just to be clear, the AM335x devices do not have a PCIe peripheral on them.

Einar Bjorgvinsson said:

But I know eventually everything has to go through the internal bus of the chip so I'm just wondering if it is a single bus communicating different peripherals inside the SoC or are there more. 

Please take a look at the AM335x Technical Reference Manual, specifically Chapter 10 entitled Interconnects.  This gives a description of the internal bus structure of the AM335x.

I'm sorry about mentioning the PCIe, I can see it was just to confuse things. 

My main concern is how the performance will be when I measure the traffic on all fronts of the AM335, i.e. SPI, CAN, I2C, USB, MMC and ETH. Is all this traffic routed inside via the same bus or does the AM335 contain multiple busses connected to different peripherals ? That is simply my question, I'm not after any technical details about implementation or anything, just want to have an idea of what is going on inside.

regards

Einar 

I will also look into chapter 10, thanks for that

regards

Einar

The internal bus structure, which is described in Chapter 10 of the Technical Reference Manual, is a crossbar switch where multiple initiators (masters) and multiple targets (slaves) are connected.  Any initiator may access a target on the switch at the same time without bottlenecks provided the initiators are not accessing the same target.

Thank you for your support, I think this answer is quite satisfactory.

Regards

Einar