• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 98 subscribers
  • Views 1415 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6678 HyperLink Debugging

Nick Landi
Prodigy 60 points


I'm attempting to verify the stability of our HyperLink on a custom board between a C6678 and Stratix IV running Integretek's HyperLink core.

I've configured the C6678 EVM HyperLink test to run 4 lanes at 1.25 Gbps per lane with 156.25 MHz synchronous clks. This reflects how I configured Integretek's HyperLink core.

The core I load the test on hangs on its first or second remote register read. This happens during the "setup peripheral" step in the EVM HyperLink test. For it to get past the first remote register read, which happens in hyplnkExampleCheckOneStat in the LLD, I need to put in a ~0.5 ms delay between Hyplnk_readRegs and Hyplnk_close.

Immediately before the core hangs, the C6678 registers are as follows:

ctl             0x00006200
--------------------------
intlocal        1
intenable       1
intvec          00010
int2cfg         0
serial_stop     0
loopback        0
reset           0

sts             0x04400005
--------------------------
swidthin        0100
swidthout       0100
serial_halt     0
pll_unlock      0
rpend           0
iflow           0
oflow           0
rerror          0
lerror          0
nfempty3        0
nfempty2        0
nfempty1        0
nfempty0        0
spend           1
mpend           0
link            1

int_pri_vec     0x80000000
--------------------------
nointpend       1
intstat         00000

pwr             0x0707004
--------------------------
h2l             111
l2h             111
pwc             00000000
highspeed       0
quadlane        1
singlelane      0
zerolane        0

link_sts        0xFDF0BDF0
--------------------------
txpls_req       11
txpls_ack       11
txpm_req        11
tx_rsync        0
txplsok         1
tx_phy_en       1111
txflow_sts      0000
rxpls_req       10
rxpls_ack       11
rxpm_req        11
rx_lsync        0
rx_one_id       1
rx_phy_en       1111
rx_phy_pol      0000

serdes_ctl_sts1 0x092E0000
--------------------------
sleep_cnt       00001001
disable_cnt     00101110

 

Are there any clues here to why the core would hang?

 

  • 0
    TI__Guru* 95265 points

    Nick,

    What is the PDK version? Does the EVM works in Hyperlink loopback mode (set iLoop bit)? Do you see "Link seems stable" before assessing the remote register? In the LLD, do you have "hyplnk_EXAMPLE_ERROR_INTERRUPT" enabled? If it is, did you see interrupt is triggered? And how EVM is connected to FPGA?

    Regards, Eric

     

  • 0 in reply to lding
    Prodigy 60 points

    What is the PDK version? 

    1.1.2.6

    Does the EVM works in Hyperlink loopback mode (set iLoop bit)?

    Yes, the EVM test runs successfully on our board when set to loopback

    Do you see "Link seems stable" before assessing the remote register?

    Yes, the EVM test doesn't attempt remote register access until after it asserts "Link seems stable"

    In the LLD, do you have "hyplnk_EXAMPLE_ERROR_INTERRUPT" enabled? If it is, did you see interrupt is triggered? 

    I had interrupts enabled and didn't see any triggered before the core hangs. I disabled interrupts and the only difference I saw was the ctl reg was 0x00000000 as oppose to 0x00006200.

    And how EVM is connected to FPGA?

    The EVM is not connected to the FPGA. This is a custom board with the C6678 connected to the FPGA by approx. 1200 mil AC coupled traces.

  • 0 in reply to Nick Landi
    TI__Guru* 95265 points

    I had test between two 6678 EVMs connected via Hyperlink cable. The registers you dumped seems right (only serdes_ctrl_sts1 differs because I used async clock). Can you try re-configure Control Register (offset 0x04) as 0x0000_6280 to see if interrupt occurred?

    Regards, Eric

  • 0 in reply to lding
    Prodigy 60 points

    No interrupts occur. I'm able to write DSP HyperLink registers remotely from the FPGA.

  • 0 in reply to Nick Landi
    TI__Guru* 95265 points

    Thanks for letting me know. It seems the Hyperlink connection is there but from DSP side you can't access the remote (FPGA) register. Are you able to read the remote register from CCS memory window? To do this, Inside hyplnkExampleCheckOneStat() function set a break point at lastCor = &lastRemoteCor;

    When it is hit, can you open a small memory window (maybe just one column) with starting address 0x2140_0000, then scroll down, when it passes the 0x2140_0080 for the first remote register, will CCS hang? If not, scroll down further and let me know if any remote register read in CCS (from 0x2140_0080 to 0x2140_00FC) hang DSP?

    Regards, Eric

  • 0 in reply to lding
    Prodigy 60 points

    Eric,

    It seems the issue is on the FPGA side. I clocked down the HyperLink core we were provided and succeeded at getting the EVM link test to pass at 4 * 3.125.

    To answer your question though, using your method of viewing remote registers always caused the core to hang. I was occasionally able to read the status register through code.

    Thanks

     

  • 0 in reply to lding
    Prodigy 10 points

    what the problem may be if i cant read the address at 0x40000000 and 0x21400000 after ininatialize the hyperlink，core hangs when i open this address in

    memoery browser？and this situation not happen every power on the system，seems like random