Example code for setting L1P, L1D and L2 cache on C6455.

Hi everyone,

I am looking for an example code setting L1P, L1D and L2 cache on C6455. This is what I want to do: upon the chip power-up or reset, I would like to set up the followings:

(1) L1P size to 32K

(2) L1D size to 32K

(3) L2 cache size to 256K

(4) Set up MAR to indicate which external memory addresses are cacheable

I have already read through this example code:

csl+3.0.10.2\csl_c6455\example\cache\src\Cache_example.c

but the example does not show the sequence of commands/functions to set up all L1 and L2 caches.