omapl138 emifa about CS

Hi Shaotu Zhu,

Thanks for your post.

In general, different sources (CPU, EDMA, master peripherals etc) will make multiple requests (access to SDRAM memory, asynchronous memory, and EMIFA registers) to EMIFA, but it can process only one request at a time, so, a high performance crossbar switch exists within the SoC to provide prioritized requests.

There is an EMIF's external prioritization and arbitration scheme among requests from different sources within the SoC. Please check Section 20.2.12 in the below OMAPL138's TRM:

http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

Note: The above mentioned priority scheme is not applicable when EMIFA is in the self-refresh state.

Thanks & regards,

Sivaraj K