Hi all,
My code base is DVRRDK_04_00_00_03 and configure platform to DM816X_UD_DVR.
I follow below link to do the DDR3 SW leveling.
http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init
But I figure out one thing, the define has conflict situation in ddr_defs_ti816x.h(DVRRDK_04.00.00.03/ti_tools/linux_lsp/uboot/u-boot-dvr-rdk/arch/arm/include/asm/arch-ti81xx). The BYTE_LANE0 corresponds to WR_DQS_LANE3, is that right? Why does not use BYTE_LANE0 to correspond to WR_DQS_LANE0? Can anyone help to clarify this portion? Thanks in advance.
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336 #if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
337 #define WR_DQS_RATIO_BYTE_LANE0 WR_DQS_LANE3
338 #define WR_DQS_RATIO_BYTE_LANE1 WR_DQS_LANE2
339 #define WR_DQS_RATIO_BYTE_LANE2 WR_DQS_LANE1
340 #define WR_DQS_RATIO_BYTE_LANE3 WR_DQS_LANE0
341
342 #define WR_DATA_RATIO_BYTE_LANE0 WR_DATA_LANE3
343 #define WR_DATA_RATIO_BYTE_LANE1 WR_DATA_LANE2
344 #define WR_DATA_RATIO_BYTE_LANE2 WR_DATA_LANE1
345 #define WR_DATA_RATIO_BYTE_LANE3 WR_DATA_LANE0
346
347 #define RD_DQS_RATIO_BYTE_LANE0 RD_DQS_LANE3
348 #define RD_DQS_RATIO_BYTE_LANE1 RD_DQS_LANE2
349 #define RD_DQS_RATIO_BYTE_LANE2 RD_DQS_LANE1
350 #define RD_DQS_RATIO_BYTE_LANE3 RD_DQS_LANE0
351
352 #define RD_DQS_GATE_BYTE_LANE0 RD_DQS_GATE_LANE3
353 #define RD_DQS_GATE_BYTE_LANE1 RD_DQS_GATE_LANE2
354 #define RD_DQS_GATE_BYTE_LANE2 RD_DQS_GATE_LANE1
355 #define RD_DQS_GATE_BYTE_LANE3 RD_DQS_GATE_LANE0
356 #endif /* CONFIG_TI816X_DDR3_SW_LEVELING */
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B.R.
OC
