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Dm368 no hsyncs

Chris Fadeley1
Intellectual 305 points
Other Parts Discussed in Thread: TVP7002

We have gotten further in development of our board and now realize we are indeed getting a VSYNC from the custom IO board.  Reading the INTSTAT register of the ISP shows the following:

00000  0800 4C18 007F 0000 0002 0000 0200 0030

Removing our IO board results in the following:

00000  0800 4C18 007F 0000 0002 0000 0000 0030

So I know it is not a false positive.  The leopardboard of course displays the following:

00000  0800 4C18 007F 0000 0002 0000 E237 00F0

So it seems we are getting a VSYNC in but not HSYNC.  We have checked the polarity of the input signal and of the ISIF sensor and both are set for active high.

The VDINTs are set properly to register at 0, 361, and 719 since it is a 720P signal.

So this seems to be implying that we aren't getting an HSYNCs at all.  We can confirm via a scope that the data is being properly sent. 

Does anyone have a hunch as to why no HSYNCs are being registered?  Any direction would help greatly.


I previously have a post running here: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/287108/1002268.aspx#1002268

If you need to look at any of my boot up messages or anything or need more information on the issue.

  • 0
    Intellectual 305 points

    I finally got to the root of the problem after a couple weeks of frustration.  Ends up the FPGA is sending the signal directly into SDRAM whereas the leopardboard doesnt.

    Hence I had to change bit 5 in ISIF's MODESET and i started getting the hsync interrupts as expected.

    We also had to change ISIF register 84 (REC656IF) because the TVP7002 part had the bits set to 1 for whatever reason.  I thought the TVP part wasn't doing any 656 but I may be mistaken.