Stopping and re-starting McASP Tx/Rx DMAs using EDMA3

The above may have been a mis-direction.

I was switching output modes for McASP between the two runs, i.e. first time McASP was configured in SPDIF mode and the second time it was configured in TDM  (non-SPDIF mode). If I force it to use the same mode during the first and second runs, I can restart and run properly. Works both for SPDIF and TDM modes.

But, the problem happens when switching modes, either going from TDM to SPDIF or SPDIF to TDM.

Any suggestions I can try?

Like I said above, I reset the McASP Tx and Rx (using McASPTxReset() and McASPRxReset() calls) at the end of first run. The reset call is there at the start of every run during configuration process also. So, McASP should be coming out of clean reset.

Does McASP reset resets the FIFOs also?

Some more bits of information

I am using Slot 0 in both TDM and SPDIF modes. So, checking for XDATA clearing should be fine according to Section 25.2.4.1.2 of OMAP-L138 TRM, I am guessing.

I could reproduce the hang even the first time if I do not enable the Write FIFO.

I am using only one serializer in the tx direction. When things work the first time (i.e. when write FIFO is enabled), the WNUMEVT and WNUMDMA are both set to 1 in WFIFOCTL register.

Why is the behavior different when write fifo is disabled?

Hi Raja,

Thanks for your post.

Basically, if the Write FIFO is disabled, transmit DMA requests passes directly from the McASP to the host/DMA controller and the AFIFO is invisible to the McASP. But, if it is enabled, transmit DMA requests from the McASP are sent to the AFIFO, which in turn generates transmit DMA requests to the host/DMA controller. In this way, the behaviour differs when you enable or disable write FIFO.

Please make sure whether WFIFOCTL.WENA is cleared to 0, if Write FIFO is not enabled when you configure McASP Audio FIFO. Note that WFIFOCTL.WENA should not be set to 1 (enabled) until the other bitfields in this register are configured.

If you configure the soft reset through the global control register (GBLCTL), only the transmitter and receiver portions of the McASP module will be put in reset and not the FIFO. Alternatively, you can also reset the entire McASP module through power and sleep controller (PSC) and this can be considered as hard reset to the entire McASP module. But, if you do the actual device reset (Hard reset), the entire serial port (including the transmitter and receiver state machines, and other registers) will be reset.

Thank you Sivaraj.

Between SPDIF mode and TDM mode, I was using different serializers. So, I had to explicitly disable one when switching modes. Another thing also was that I had to turn off DIT mode when switching to TDM mode. I am guessing disabling PSC might have done that as well. Will give that a try when I get some time. But, I am okay for now with the above mentioned changes.

I am still unable to get things to work with FIFO disabled.

Hi Raja,

Thanks for your update.

I think, your guess is correct. Please give it a try and let me know your input on the same.

Thanks & regards,

Sivaraj K