Hello all,
my platform is AM335x platform,and BSP version is based on BSP version(ti-sdk-am335x-evm-05.05.00.00) ,kernel version is linux-3.2.0-psp04.06.00.08;
I use AM335x PWM function (or other DMTimer) to let ehrpwm2.0 output a duty 1us and period 300us fixed pulse ,and add a PWM ISR at linux kernel
we set the situation when the PWM output a complete pulse ,and PWM ISR (Interrupt Number:39)will be executed ,and it seems ok and well at normal condition of linux environment ,
we use the scope to measure the time between PWM output a complete pulse and PWM ISR been executed ,normally, 4 ~ 8 us is the time between PWM output a complete pulse and PWM ISR will be executed
but,when we execute other appliction (like 3D graphics benchmark program ) at the same time,such that the system overloading becomes larger,the time between PWM output a complete pulse and PWM ISR been executed sometimes will be prolong to 30 ~ 58 us ,we cannot accept it ,
when we treat PWM ISR(or DMTimer ISR) as 1st Priority Interrupt handler to deal with important thing
As we know ,AM335x Interrupt Mechaniam is non-preemptive interrupt mechanism ,i.e.
the register INTC_THRESHOLD[PRIORITYTHRESHOLD] always keep oxff ,
so,my questions are
(1) Whether does interrupt mechanism been changed from non-preemptive to preemptive can avoid upper question ?
when we treams PWM ISR(or DMTimer4 ISR) is a very important Interupt hanlder,and the delay between hardware interupt (currently,is PWM interrupt) happened and hardware ISR (currently,is PWM ISR) been executed must keep under or around 10us ?
(2) Base on AM335x TRM 6.2.3 INTC Preemptive Processing Sequence,
How to implemnt preemptive interrupt ? Is there patch for preemptive interrupt such that we can refer to ?
because currenly we use kernel version is linux-3.2.0-psp04.06.00.08 as code base,
and it is a little difficult to implemnt this at short time
Best Regards